The Experts below are selected from a list of 582 Experts worldwide ranked by ideXlab platform
Ingrid Verbauwhede - One of the best experts on this subject based on the ideXlab platform.
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14.1 A Side-Channel Leakage Free Coprocessor IC in 0.18µm CMOS for Embedded AES-based Cryptographic and Biometric Processing
2013Co-Authors: Kris Tiri, A Hodjat, Patrick Schaumont, Bc Lai, Sl Yang, D. Hwang, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18µm CMOS. The coprocessor, which is used for embedded Cryptographic and biometric processing, consists of four components: an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching oracle, a template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first, ‘secure’, coprocessor is implemented using a logic style called Wave Dynamic Digital Logic (WDDL) and a layout technique called differential routing. The second, ‘insecure’, coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems
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AES-Based Security Coprocessor IC in 0.18-"m CMOS With Resistance to Differential Power Analysis Side-Channel Attacks
2008Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Student Member, Ingrid VerbauwhedeAbstract:Abstract—Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- m CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions. Index Terms—Advanced Encryption Standard (AES), biometrics, cryptography, differential power analysis, security, side-channel attacks. I
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aes based security coprocessor ic in 0 18 muhbox m cmos with resistance to differential power analysis side channel attacks
IEEE Journal of Solid-state Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- $muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based security coprocessor ic in 0 18 μm cmos with resistance to differential power analysis side channel attacks
Symposium on VLSI Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based Cryptographic and biometric security coprocessor ic in 0 18 spl mu m cmos resistant to side channel power analysis attacks
Symposium on VLSI Circuits, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:This paper describes an embedded security coprocessor that consists of four components: an advanced encryption standard (AES) based Cryptographic Engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical coprocessors are fabricated using a TSMC 6M 0.18-/spl mu/m process. The first coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second coprocessor uses wave dynamic differential logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The coprocessor is part of a security-partitioned embedded system called ThumbPod.
Kris Tiri - One of the best experts on this subject based on the ideXlab platform.
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14.1 A Side-Channel Leakage Free Coprocessor IC in 0.18µm CMOS for Embedded AES-based Cryptographic and Biometric Processing
2013Co-Authors: Kris Tiri, A Hodjat, Patrick Schaumont, Bc Lai, Sl Yang, D. Hwang, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18µm CMOS. The coprocessor, which is used for embedded Cryptographic and biometric processing, consists of four components: an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching oracle, a template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first, ‘secure’, coprocessor is implemented using a logic style called Wave Dynamic Digital Logic (WDDL) and a layout technique called differential routing. The second, ‘insecure’, coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems
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AES-Based Security Coprocessor IC in 0.18-"m CMOS With Resistance to Differential Power Analysis Side-Channel Attacks
2008Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Student Member, Ingrid VerbauwhedeAbstract:Abstract—Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- m CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions. Index Terms—Advanced Encryption Standard (AES), biometrics, cryptography, differential power analysis, security, side-channel attacks. I
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aes based security coprocessor ic in 0 18 muhbox m cmos with resistance to differential power analysis side channel attacks
IEEE Journal of Solid-state Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- $muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based security coprocessor ic in 0 18 μm cmos with resistance to differential power analysis side channel attacks
Symposium on VLSI Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based Cryptographic and biometric security coprocessor ic in 0 18 spl mu m cmos resistant to side channel power analysis attacks
Symposium on VLSI Circuits, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:This paper describes an embedded security coprocessor that consists of four components: an advanced encryption standard (AES) based Cryptographic Engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical coprocessors are fabricated using a TSMC 6M 0.18-/spl mu/m process. The first coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second coprocessor uses wave dynamic differential logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The coprocessor is part of a security-partitioned embedded system called ThumbPod.
D D Hwang - One of the best experts on this subject based on the ideXlab platform.
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AES-Based Security Coprocessor IC in 0.18-"m CMOS With Resistance to Differential Power Analysis Side-Channel Attacks
2008Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Student Member, Ingrid VerbauwhedeAbstract:Abstract—Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- m CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions. Index Terms—Advanced Encryption Standard (AES), biometrics, cryptography, differential power analysis, security, side-channel attacks. I
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aes based security coprocessor ic in 0 18 muhbox m cmos with resistance to differential power analysis side channel attacks
IEEE Journal of Solid-state Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- $muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based security coprocessor ic in 0 18 μm cmos with resistance to differential power analysis side channel attacks
Symposium on VLSI Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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AES-Based Security Coprocessor IC in 0.18-um CMOS with Resistance to Differential Power Analysis Side-Channel Attacks
'Institute of Electrical and Electronics Engineers (IEEE)', 2006Co-Authors: D D Hwang, Tiri K, Hodjat A, Bc Lai, Sl Yang, Schallmont P, Verbauwhede IngridAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-mu m CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1500 000 encryptions.status: publishe
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aes based Cryptographic and biometric security coprocessor ic in 0 18 spl mu m cmos resistant to side channel power analysis attacks
Symposium on VLSI Circuits, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:This paper describes an embedded security coprocessor that consists of four components: an advanced encryption standard (AES) based Cryptographic Engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical coprocessors are fabricated using a TSMC 6M 0.18-/spl mu/m process. The first coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second coprocessor uses wave dynamic differential logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The coprocessor is part of a security-partitioned embedded system called ThumbPod.
Patrick Schaumont - One of the best experts on this subject based on the ideXlab platform.
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14.1 A Side-Channel Leakage Free Coprocessor IC in 0.18µm CMOS for Embedded AES-based Cryptographic and Biometric Processing
2013Co-Authors: Kris Tiri, A Hodjat, Patrick Schaumont, Bc Lai, Sl Yang, D. Hwang, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18µm CMOS. The coprocessor, which is used for embedded Cryptographic and biometric processing, consists of four components: an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching oracle, a template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first, ‘secure’, coprocessor is implemented using a logic style called Wave Dynamic Digital Logic (WDDL) and a layout technique called differential routing. The second, ‘insecure’, coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems
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AES-Based Security Coprocessor IC in 0.18-"m CMOS With Resistance to Differential Power Analysis Side-Channel Attacks
2008Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Student Member, Ingrid VerbauwhedeAbstract:Abstract—Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- m CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions. Index Terms—Advanced Encryption Standard (AES), biometrics, cryptography, differential power analysis, security, side-channel attacks. I
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aes based security coprocessor ic in 0 18 muhbox m cmos with resistance to differential power analysis side channel attacks
IEEE Journal of Solid-state Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- $muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based security coprocessor ic in 0 18 μm cmos with resistance to differential power analysis side channel attacks
Symposium on VLSI Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based Cryptographic and biometric security coprocessor ic in 0 18 spl mu m cmos resistant to side channel power analysis attacks
Symposium on VLSI Circuits, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:This paper describes an embedded security coprocessor that consists of four components: an advanced encryption standard (AES) based Cryptographic Engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical coprocessors are fabricated using a TSMC 6M 0.18-/spl mu/m process. The first coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second coprocessor uses wave dynamic differential logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The coprocessor is part of a security-partitioned embedded system called ThumbPod.
A Hodjat - One of the best experts on this subject based on the ideXlab platform.
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14.1 A Side-Channel Leakage Free Coprocessor IC in 0.18µm CMOS for Embedded AES-based Cryptographic and Biometric Processing
2013Co-Authors: Kris Tiri, A Hodjat, Patrick Schaumont, Bc Lai, Sl Yang, D. Hwang, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18µm CMOS. The coprocessor, which is used for embedded Cryptographic and biometric processing, consists of four components: an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching oracle, a template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first, ‘secure’, coprocessor is implemented using a logic style called Wave Dynamic Digital Logic (WDDL) and a layout technique called differential routing. The second, ‘insecure’, coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems
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AES-Based Security Coprocessor IC in 0.18-"m CMOS With Resistance to Differential Power Analysis Side-Channel Attacks
2008Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Student Member, Ingrid VerbauwhedeAbstract:Abstract—Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- m CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions. Index Terms—Advanced Encryption Standard (AES), biometrics, cryptography, differential power analysis, security, side-channel attacks. I
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aes based security coprocessor ic in 0 18 muhbox m cmos with resistance to differential power analysis side channel attacks
IEEE Journal of Solid-state Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- $muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based security coprocessor ic in 0 18 μm cmos with resistance to differential power analysis side channel attacks
Symposium on VLSI Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based Cryptographic Engine, a fingerprint-matching Engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based Cryptographic and biometric security coprocessor ic in 0 18 spl mu m cmos resistant to side channel power analysis attacks
Symposium on VLSI Circuits, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:This paper describes an embedded security coprocessor that consists of four components: an advanced encryption standard (AES) based Cryptographic Engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical coprocessors are fabricated using a TSMC 6M 0.18-/spl mu/m process. The first coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second coprocessor uses wave dynamic differential logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The coprocessor is part of a security-partitioned embedded system called ThumbPod.