The Experts below are selected from a list of 4563 Experts worldwide ranked by ideXlab platform
Soonhoi Ha - One of the best experts on this subject based on the ideXlab platform.
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Memory optimal single appearance schedule with dynamic loop count for synchronous Dataflow graphs
Asia and South Pacific Conference on Design Automation 2006., 2006Co-Authors: Hyunok Oh, Nikil Dutt, Soonhoi HaAbstract:In this paper, we propose a new single appearance schedule for synchronous Dataflow programs to minimize Data Memory and code Memory size at the same time. When the software code is automatically synthesized from the Dataflow program graphs, a single appearance schedule promises only one appearance of each node definition in the generated code. While several heuristics have been developed to find a single appearance schedule, they all have to pay significant amount of Data Memory overhead compared with a buffer optimal schedule. The key idea of the proposed technique is to make a dynamic decision of loop count to make a schedule quasi-static. The proposed quasi-static static schedule produces a single appearance schedule code with minimum Data Memory requirement. We prove that the proposed scheduling technique is optimal for a chain-structured graph in terms of Data Memory requirement while maintaining the single appearance schedule. The only penalty for the proposed technique is slight performance overhead of computing loop counts dynamically. Experimental results show that the proposed algorithm reduces 20% total Memory with less than 1% performance overhead compared with the previous single appearance schedule algorithms for CD2DAT and non uniform filter bank applications. Copyright 2005 ACM.
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CASES - Single appearance schedule with dynamic loop count for minimum Data buffer from synchronous Dataflow graphs
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Hyunok Oh, Nikil Dutt, Soonhoi HaAbstract:In this paper, we propose a new single appearance schedule for synchronous Dataflow programs to minimize Data Memory and code Memory size at the same time. When the software code is automatically synthesized from the Dataflow program graphs, a single appearance schedule promises only one appearance of each node definition in the generated code. While several heuristics have been developed to find a single appearance schedule, they all have to pay significant amount of Data Memory overhead compared with a buffer optimal schedule. The key idea of the proposed technique is to make a dynamic decision of loop count to make a schedule quasi-static. The proposed quasi-static static schedule produces a single appearance schedule code with minimum Data Memory requirement. We prove that the proposed scheduling technique is optimal for a chain-structured graph in terms of Data Memory requirement while maintaining the single appearance schedule. The only penalty for the proposed technique is slight performance overhead of computing loop counts dynamically. Experimental results show that the proposed algorithm reduces 20% total Memory with less than 1% performance overhead compared with the previous single appearance schedule algorithms for CD2DAT and non uniform filter bank applications.
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ASP-DAC - Data Memory minimization by sharing large size buffers
Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00, 2000Co-Authors: Hyunok Oh, Soonhoi HaAbstract:This paper presents software synthesis techniques to deal with non-primitive Data type from graphical Dataflow programs based on the synchronous Dataflow (SDF) model. Non-primitive Data types, often used in multimedia and graphics applications, require buffer Memory of large size. To minimize the buffer requirement, we separate global Data buffers and local pointer buffers. The proposed approach first allocates the minimum size of global buffers and next binds the local buffers to the global buffers by setting the pointers. Static binding and dynamic binding techniques are devised. Experimental results prove the significance of the proposed techniques.
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Data Memory minimization by sharing large size buffers
Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106), 2000Co-Authors: Hyunok Oh, Soonhoi HaAbstract:This paper presents software synthesis techniques to deal with non-primitive Data type from graphical Dataflow programs based on the synchronous Dataflow (SDF) model. Non-primitive Data types, often used in multimedia and graphics applications, require buffer Memory of large size. To minimize the buffer requirement, we separate global Data buffers and local pointer buffers. The proposed approach first allocates the minimum size of global buffers and next binds the local buffers to the global buffers by setting the pointers. Static binding and dynamic binding techniques are devised. Experimental results prove the significance of the proposed techniques.
Hyunok Oh - One of the best experts on this subject based on the ideXlab platform.
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Memory optimal single appearance schedule with dynamic loop count for synchronous Dataflow graphs
Asia and South Pacific Conference on Design Automation 2006., 2006Co-Authors: Hyunok Oh, Nikil Dutt, Soonhoi HaAbstract:In this paper, we propose a new single appearance schedule for synchronous Dataflow programs to minimize Data Memory and code Memory size at the same time. When the software code is automatically synthesized from the Dataflow program graphs, a single appearance schedule promises only one appearance of each node definition in the generated code. While several heuristics have been developed to find a single appearance schedule, they all have to pay significant amount of Data Memory overhead compared with a buffer optimal schedule. The key idea of the proposed technique is to make a dynamic decision of loop count to make a schedule quasi-static. The proposed quasi-static static schedule produces a single appearance schedule code with minimum Data Memory requirement. We prove that the proposed scheduling technique is optimal for a chain-structured graph in terms of Data Memory requirement while maintaining the single appearance schedule. The only penalty for the proposed technique is slight performance overhead of computing loop counts dynamically. Experimental results show that the proposed algorithm reduces 20% total Memory with less than 1% performance overhead compared with the previous single appearance schedule algorithms for CD2DAT and non uniform filter bank applications. Copyright 2005 ACM.
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CASES - Single appearance schedule with dynamic loop count for minimum Data buffer from synchronous Dataflow graphs
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Hyunok Oh, Nikil Dutt, Soonhoi HaAbstract:In this paper, we propose a new single appearance schedule for synchronous Dataflow programs to minimize Data Memory and code Memory size at the same time. When the software code is automatically synthesized from the Dataflow program graphs, a single appearance schedule promises only one appearance of each node definition in the generated code. While several heuristics have been developed to find a single appearance schedule, they all have to pay significant amount of Data Memory overhead compared with a buffer optimal schedule. The key idea of the proposed technique is to make a dynamic decision of loop count to make a schedule quasi-static. The proposed quasi-static static schedule produces a single appearance schedule code with minimum Data Memory requirement. We prove that the proposed scheduling technique is optimal for a chain-structured graph in terms of Data Memory requirement while maintaining the single appearance schedule. The only penalty for the proposed technique is slight performance overhead of computing loop counts dynamically. Experimental results show that the proposed algorithm reduces 20% total Memory with less than 1% performance overhead compared with the previous single appearance schedule algorithms for CD2DAT and non uniform filter bank applications.
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ASP-DAC - Data Memory minimization by sharing large size buffers
Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00, 2000Co-Authors: Hyunok Oh, Soonhoi HaAbstract:This paper presents software synthesis techniques to deal with non-primitive Data type from graphical Dataflow programs based on the synchronous Dataflow (SDF) model. Non-primitive Data types, often used in multimedia and graphics applications, require buffer Memory of large size. To minimize the buffer requirement, we separate global Data buffers and local pointer buffers. The proposed approach first allocates the minimum size of global buffers and next binds the local buffers to the global buffers by setting the pointers. Static binding and dynamic binding techniques are devised. Experimental results prove the significance of the proposed techniques.
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Data Memory minimization by sharing large size buffers
Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106), 2000Co-Authors: Hyunok Oh, Soonhoi HaAbstract:This paper presents software synthesis techniques to deal with non-primitive Data type from graphical Dataflow programs based on the synchronous Dataflow (SDF) model. Non-primitive Data types, often used in multimedia and graphics applications, require buffer Memory of large size. To minimize the buffer requirement, we separate global Data buffers and local pointer buffers. The proposed approach first allocates the minimum size of global buffers and next binds the local buffers to the global buffers by setting the pointers. Static binding and dynamic binding techniques are devised. Experimental results prove the significance of the proposed techniques.
Margarida F. Jacome - One of the best experts on this subject based on the ideXlab platform.
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Energy-Delay Efficient Data Memory Subsystems
2020Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:Data Memory subsystems play a key role in the energy-delay efficiency of streaming media applications. In this article, we present a novel special-purpose Data Memory subsystem, Xtream-Fit, and demonstrate how it achieves high energy-delay efficiency across a wide range of media devices, including systems concurrently executing multiple applications under synchronization constraints. The effectiveness of Xtream-Fit relies on both the use of on-chip software-controlled memories and a novel taskbased execution model. These features enable efficient Data prefetching and aggressive dynamic energy conservation policies, targeting on-chip and off-chip Memory components. A key additional advantage of Xtream-Fit with respect to traditional cache-based Memory subsystems is that it exposes a single customization parameter per application, thus enabling a very simple yet effective tuning methodology. We present extensive experimental results, empirically demonstrating that Xtream-Fit reduces energy-delay products by 43‐72%, compared to general-purpose Memory subsystems enhanced with state-of-the-art cache-decay and SDRAM power-mode control policies.
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Xtream-fit: an energy-delay efficient Data Memory subsystem for embedded media processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:Due to the critical role played by Data Memory subsystems in the performance and energy efficiency of embedded systems, the design of energy-efficient Data Memory architectures has received considerable attention in recent years. In this paper, we propose a novel special-purpose Data Memory subsystem called Xtream-Fit which is aimed at achieving high energy-delay efficiency for streaming media applications. A key novelty of Xtream-Fit is that it exposes a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology. A second key contribution of this paper is the ability to achieve very high energy-delay efficiency through a synergistic combination of: 1) special purpose Memory subsystem components, namely, a streaming Memory and a scratch-pad Memory and (2) a novel task-based execution model that exposes/enhances opportunities for efficient prefetching, and aggressive dynamic energy conservation techniques targeting on-chip and off-chip Memory components. Extensive experimental results show that Xtream-Fit reduces the energy-delay product by 22% to 61%, as compared to general-purpose Memory subsystems enhanced with state of the art cache decay and SDRAM power-mode control policies.
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Energy-delay efficient Data Memory subsystems: suitable for embedded media "processing"
IEEE Signal Processing Magazine, 2005Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:This article presents a novel special-purpose Data Memory subsystem, called Xtream-Fit, suitable for embedded media processing, and demonstrates how it achieves high energy-delay efficiency across a wide range of media devices, including systems concurrently executing multiple applications under synchronization constraints. Experimental results show that Xtream-Fit delivers a substantial improvement in energy-delay product, as compared to general-purpose Memory subsystems enhanced with state of-the-art cache decay and SDRAM dynamic power mode control policies. Xtreams-Fit's performance is predicted on a novel, task-based execution model that enhances opportunities for efficient stream granularity prefetching and aggressive software-based energy conservation techniques.
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Xtream-fit: an energy-delay efficient Data Memory subsystem for embedded media processing
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), 2003Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:In this paper, we propose a novel special-purpose Data Memory subsystem, called Xtream-fit, aimed at achieving high-energy-delay efficiency for streaming media applications. A key novelty of Xtream-fit is that it exposes a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology. A second key contribution of this work is the ability to achieve very high energy-delay efficiency through a synergistic combination of: (1) special purpose Memory subsystem components, namely, a streaming Memory and scratch-pad Memory; and (2) a novel task-based execution model that exposes/enhances opportunities for efficient prefetching and aggressive dynamic energy conservation techniques targeting on-chip and off-chip Memory components. Extensive experimental results show that Xtream-fit reduces energy-delay product by 46% to 83%, as compared to general-purpose Memory subsystems enhanced with state of the art cache decay and SDRAM power mode control policies.
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DAC - Xtream-fit: an energy-delay efficient Data Memory subsystem for embedded media processing
Proceedings of the 40th conference on Design automation - DAC '03, 2003Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:In this paper we propose a novel special-purpose Data Memory subsystem, called Xtream-Fit, aimed at achieving high energy-delay efficiency for streaming media applications. A key novelty of Xtream-Fit is that it exposes a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology. A second key contribution of this work is the ability to achieve very high energy-delay efficiency through a synergistic combination of: (1) special purpose Memory subsystem components, namely, a Streaming Memory and Scratch-Pad Memory; and (2) a novel task-based execution model that exposes/enhances opportunities for efficient prefetching, and aggressive dynamic energy conservation techniques targeting on-chip and off-chip Memory components. Extensive experimental results show that Xtream-Fit reduces energy-delay product by 46% to 83%, as compared to general-purpose Memory subsystems enhanced with state of the art Cache Decay and SDRAM power mode control policies.
J. Tanskanen - One of the best experts on this subject based on the ideXlab platform.
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EUSIPCO - Verifying external Data Memory interface for H.263 video DSP with Memory simulator
2000Co-Authors: J. Alakarhu, J. Niittylahti, T. Sihvo, J. TanskanenAbstract:In this paper, we present the simulator-based method to estimate the time required by the external Data Memory accesses in the H.263 video encoding. Different frame rates and picture resolutions are considered. The Video DSP structure considered here consists of several parallel on-chip DSP units and it is optimized for the H.263 video encoding. Execution time is coarsely divided between control/non-sequential processing, parallel processing, and external Data Memory traffic. To evaluate the performance in early design phase, one must find out the time required by each part. The Memory simulator method described here gives an estimate of the time required by the external Memory accesses. With this estimate, one can also make sure that the proposed partitioning between internal and external Data memories is correct and the required Memory bandwidth for the external Data Memory is not too high.
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Verifying external Data Memory interface for H.263 video DSP with Memory simulator
2000 10th European Signal Processing Conference, 2000Co-Authors: J. Alakarhu, J. Niittylahti, T. Sihvo, J. TanskanenAbstract:In this paper, we present the simulator-based method to estimate the time required by the external Data Memory accesses in the H.263 video encoding. Different frame rates and picture resolutions are considered. The Video DSP structure considered here consists of several parallel on-chip DSP units and it is optimized for the H.263 video encoding. Execution time is coarsely divided between control/non-sequential processing, parallel processing, and external Data Memory traffic. To evaluate the performance in early design phase, one must find out the time required by each part. The Memory simulator method described here gives an estimate of the time required by the external Memory accesses. With this estimate, one can also make sure that the proposed partitioning between internal and external Data memories is correct and the required Memory bandwidth for the external Data Memory is not too high.
Anand Ramachandran - One of the best experts on this subject based on the ideXlab platform.
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Energy-Delay Efficient Data Memory Subsystems
2020Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:Data Memory subsystems play a key role in the energy-delay efficiency of streaming media applications. In this article, we present a novel special-purpose Data Memory subsystem, Xtream-Fit, and demonstrate how it achieves high energy-delay efficiency across a wide range of media devices, including systems concurrently executing multiple applications under synchronization constraints. The effectiveness of Xtream-Fit relies on both the use of on-chip software-controlled memories and a novel taskbased execution model. These features enable efficient Data prefetching and aggressive dynamic energy conservation policies, targeting on-chip and off-chip Memory components. A key additional advantage of Xtream-Fit with respect to traditional cache-based Memory subsystems is that it exposes a single customization parameter per application, thus enabling a very simple yet effective tuning methodology. We present extensive experimental results, empirically demonstrating that Xtream-Fit reduces energy-delay products by 43‐72%, compared to general-purpose Memory subsystems enhanced with state-of-the-art cache-decay and SDRAM power-mode control policies.
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Xtream-fit: an energy-delay efficient Data Memory subsystem for embedded media processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:Due to the critical role played by Data Memory subsystems in the performance and energy efficiency of embedded systems, the design of energy-efficient Data Memory architectures has received considerable attention in recent years. In this paper, we propose a novel special-purpose Data Memory subsystem called Xtream-Fit which is aimed at achieving high energy-delay efficiency for streaming media applications. A key novelty of Xtream-Fit is that it exposes a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology. A second key contribution of this paper is the ability to achieve very high energy-delay efficiency through a synergistic combination of: 1) special purpose Memory subsystem components, namely, a streaming Memory and a scratch-pad Memory and (2) a novel task-based execution model that exposes/enhances opportunities for efficient prefetching, and aggressive dynamic energy conservation techniques targeting on-chip and off-chip Memory components. Extensive experimental results show that Xtream-Fit reduces the energy-delay product by 22% to 61%, as compared to general-purpose Memory subsystems enhanced with state of the art cache decay and SDRAM power-mode control policies.
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Energy-delay efficient Data Memory subsystems: suitable for embedded media "processing"
IEEE Signal Processing Magazine, 2005Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:This article presents a novel special-purpose Data Memory subsystem, called Xtream-Fit, suitable for embedded media processing, and demonstrates how it achieves high energy-delay efficiency across a wide range of media devices, including systems concurrently executing multiple applications under synchronization constraints. Experimental results show that Xtream-Fit delivers a substantial improvement in energy-delay product, as compared to general-purpose Memory subsystems enhanced with state of-the-art cache decay and SDRAM dynamic power mode control policies. Xtreams-Fit's performance is predicted on a novel, task-based execution model that enhances opportunities for efficient stream granularity prefetching and aggressive software-based energy conservation techniques.
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Xtream-fit: an energy-delay efficient Data Memory subsystem for embedded media processing
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), 2003Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:In this paper, we propose a novel special-purpose Data Memory subsystem, called Xtream-fit, aimed at achieving high-energy-delay efficiency for streaming media applications. A key novelty of Xtream-fit is that it exposes a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology. A second key contribution of this work is the ability to achieve very high energy-delay efficiency through a synergistic combination of: (1) special purpose Memory subsystem components, namely, a streaming Memory and scratch-pad Memory; and (2) a novel task-based execution model that exposes/enhances opportunities for efficient prefetching and aggressive dynamic energy conservation techniques targeting on-chip and off-chip Memory components. Extensive experimental results show that Xtream-fit reduces energy-delay product by 46% to 83%, as compared to general-purpose Memory subsystems enhanced with state of the art cache decay and SDRAM power mode control policies.
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DAC - Xtream-fit: an energy-delay efficient Data Memory subsystem for embedded media processing
Proceedings of the 40th conference on Design automation - DAC '03, 2003Co-Authors: Anand Ramachandran, Margarida F. JacomeAbstract:In this paper we propose a novel special-purpose Data Memory subsystem, called Xtream-Fit, aimed at achieving high energy-delay efficiency for streaming media applications. A key novelty of Xtream-Fit is that it exposes a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology. A second key contribution of this work is the ability to achieve very high energy-delay efficiency through a synergistic combination of: (1) special purpose Memory subsystem components, namely, a Streaming Memory and Scratch-Pad Memory; and (2) a novel task-based execution model that exposes/enhances opportunities for efficient prefetching, and aggressive dynamic energy conservation techniques targeting on-chip and off-chip Memory components. Extensive experimental results show that Xtream-Fit reduces energy-delay product by 46% to 83%, as compared to general-purpose Memory subsystems enhanced with state of the art Cache Decay and SDRAM power mode control policies.
