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Seon-hwan Hwang - One of the best experts on this subject based on the ideXlab platform.

  • Dc Offset Compensation Algorithm in the Grid Voltage of Single-phase Grid-connected Inverter
    2019 IEEE Applied Power Electronics Conference and Exposition (APEC), 2019
    Co-Authors: Seon-hwan Hwang, Jong-won Park
    Abstract:

    This paper presents the Dc Offset compensation algorithm in the measured grid voltage of single-phase grid-connected inverter. When including the Dc Offset at the measured grid voltage, the estimated grid frequency and grid-side current might be distorted. In this paper, SRF-PLL is used to generate the grid angle information and the effects of the Dc Offset are analyzed in detailed. Due to the Dc Offset, the estimated phase angle includes the specific harmonic component which is the fundamental frequency of the grid frequency. As a result, in this paper, the measured grid voltage including the Dc Offset is compensated by using the synchronous reference frame with high pass filter and all pass filter. The experimental results are presented to demonstrate the effectiveness of the proposed algorithm.

  • Dc Offset Error Compensation for Synchronous Reference Frame PLL in Single-Phase Grid-Connected Converters
    IEEE Transactions on Power Electronics, 2012
    Co-Authors: Seon-hwan Hwang, Hui Li
    Abstract:

    This letter proposes a Dc Offset error compensation algorithm for synchronous reference frame phase-locked loop (PLL) in single-phase grid-connected converters. The errors generated from the grid voltage measurement circuits can be divided into Dc Offset and scaling errors. These errors may cause the undesirable periodic ripples with grid frequency in the synchronous reference frame PLL. As a result, the performance of the power conversion systems is degraded. In this letter, the effects of the Dc Offset and scaling errors are comprehensively analyzed based on the synchronous dq frame PLL. In particular, the Dc Offset error can be estimated and compensated by controlling the synchronous d-axis voltage in a PLL system to be zero. The proposed algorithm does not require any additional hardware and can be implemented by a simple proportional-integral controller and an integral operation. Experimental results are presented to demonstrate the effective- ness of the proposed Dc Offset error compensation algorithm.

Jong-won Park - One of the best experts on this subject based on the ideXlab platform.

  • Dc Offset Compensation Algorithm in the Grid Voltage of Single-phase Grid-connected Inverter
    2019 IEEE Applied Power Electronics Conference and Exposition (APEC), 2019
    Co-Authors: Seon-hwan Hwang, Jong-won Park
    Abstract:

    This paper presents the Dc Offset compensation algorithm in the measured grid voltage of single-phase grid-connected inverter. When including the Dc Offset at the measured grid voltage, the estimated grid frequency and grid-side current might be distorted. In this paper, SRF-PLL is used to generate the grid angle information and the effects of the Dc Offset are analyzed in detailed. Due to the Dc Offset, the estimated phase angle includes the specific harmonic component which is the fundamental frequency of the grid frequency. As a result, in this paper, the measured grid voltage including the Dc Offset is compensated by using the synchronous reference frame with high pass filter and all pass filter. The experimental results are presented to demonstrate the effectiveness of the proposed algorithm.

Hui Li - One of the best experts on this subject based on the ideXlab platform.

  • Dc Offset Error Compensation for Synchronous Reference Frame PLL in Single-Phase Grid-Connected Converters
    IEEE Transactions on Power Electronics, 2012
    Co-Authors: Seon-hwan Hwang, Hui Li
    Abstract:

    This letter proposes a Dc Offset error compensation algorithm for synchronous reference frame phase-locked loop (PLL) in single-phase grid-connected converters. The errors generated from the grid voltage measurement circuits can be divided into Dc Offset and scaling errors. These errors may cause the undesirable periodic ripples with grid frequency in the synchronous reference frame PLL. As a result, the performance of the power conversion systems is degraded. In this letter, the effects of the Dc Offset and scaling errors are comprehensively analyzed based on the synchronous dq frame PLL. In particular, the Dc Offset error can be estimated and compensated by controlling the synchronous d-axis voltage in a PLL system to be zero. The proposed algorithm does not require any additional hardware and can be implemented by a simple proportional-integral controller and an integral operation. Experimental results are presented to demonstrate the effective- ness of the proposed Dc Offset error compensation algorithm.

Mohamed Benbouzid - One of the best experts on this subject based on the ideXlab platform.

  • low pass filtering or gain tuning free simple Dc Offset rejection technique for single and three phase systems
    Electric Power Systems Research, 2020
    Co-Authors: Hafiz Ahmed, Mohamed Benbouzid, Samet Biricik
    Abstract:

    Abstract This paper aims to address the Dc Offset rejection problem in grid synchronization algorithm. A simple approach to estimate the unknown grid frequency in the presence of Dc Offset is proposed for this purpose. Some of the existing techniques available in the literature use either low-pass filter or an additional integrator to eliminate the Dc Offset. Both approaches require an additional parameter to tune. However, tuning the additional parameter is not straightforward. Moreover, tuning the overall system can be complicated due to the presence of Dc Offset rejection part. The proposed approach does not require any additional parameter to tune. By considering the orthogonal signal instead of the Dc Offset as an additional state, the proposed technique can efficiently estimate the unknown frequency of the grid. Application to both single and three-phase grids are provided. Comparative experimental results with Dc Offset rejection capable second-order generalized integrator (SOGI) phase-locked loop (PLL) (SOGI-PLL) demonstrate the effectiveness and suitability of the proposed technique.

  • demodulation type single phase pll with Dc Offset rejection
    Electronics Letters, 2020
    Co-Authors: Hafiz Ahmed, Mohamed Benbouzid
    Abstract:

    This Letter proposes demodulation type PLL for phase and frequency estimation of single-phase system that can reject Dc Offset. Using results from the adaptive estimation literature, this Letter proposes a linear parametric model-based initial phase angle estimation approach. Then by using differentiation and integration operation on the estimated initial phase angle, the frequency is estimated. This avoids the use of any low-pass filter unlike conventional demodulation-based technique. Moreover, unlike existing demodulation-based technique, the proposed technique can completely reject Dc Offset. Comparative experimental results, provided with state-of-the-art Dc Offset rejection-based enhanced phase locked-loop, clearly demonstrate the suitability of the proposed technique.

Changzhi Li - One of the best experts on this subject based on the ideXlab platform.

  • A Dc-Coupled High Dynamic Range Biomedical Radar Sensor With Fast-Settling Analog Dc Offset Cancelation
    IEEE Transactions on Instrumentation and Measurement, 2019
    Co-Authors: Dongyang Tang, Weibo Hu, Zhengyu Peng, Yi-chyun Chiang, Jing Wang, Changzhi Li
    Abstract:

    One challenge of designing a Dc-coupled biomedical radar sensor is dealing with the Dc Offset voltage presented in its receiver. The undesired Dc Offset is mainly caused by clutter reflection and hardware imperfection. It may saturate the baseband amplifier and limit the maximum dynamic range that a biomedical radar sensor can achieve. AC-coupling the signal can eliminate Dc Offset but it will also distort the signal, and thus may not be acceptable for high precision applications. In this paper, a Dc-coupled biomedical radar sensor is proposed incorporating an analog Dc Offset cancellation circuit with fast start-up feature. It can automatically remove any Dc Offset in the baseband signal and emulates an ac-coupling system. It can also be easily reconfigured into a Dc-tracking mode when application requires. When entering this mode, the initial Dc Offset will be removed, whereas future Dc change can be recorded. The proposed solution only uses analog components without requiring any digital signal processing nor software programming. Therefore, compared with the existing digitized Dc Offset calibration techniques, the proposed method has the advantage of low cost, easy implementation, short delay, and high resolution. The experiment results demonstrated that a wide range of Dc Offset can be successfully removed from the biomedical radar sensor, and its dynamic range can be maximized. The reconfiguration of the Dc-tracking mode has also been tested and verified. Furthermore, the proposed Dc Offset cancellation circuit has the potential to be easily adopted by other systems that also face the Dc Offset problem.

  • A Portable Doppler/FSK/FMCW Multi-mode Radar With Analog Dc Offset Cancellation for Biomedical Applications
    2019 United States National Committee of URSI National Radio Science Meeting (USNC-URSI NRSM), 2019
    Co-Authors: Jing Wang, Changzhi Li
    Abstract:

    This paper presents an integrated portable multi-mode radar system incorporating Doppler, frequency-shift keying (FSK), and frequency-modulated continuous-wave (FMCW) modes with an analog Dc Offset baseband cancellation circuit. The proposed radar system can be used for various biomedical applications such as non-contact vital signs monitoring, fall detection, and human tracking. A common problem of biomedical radar sensors is the Dc Offset presented at the output of the mixer caused by hardware imperfection and reflections from nearby stationary objects. This leads to signal distortion, baseband amplifier saturation, and dynamic range reduction. Therefore, an analog Dc Offset cancellation circuit is integrated to automatically and continuously remove the Dc Offset before baseband amplification. Experiment results of different modes are reported to demonstrate the multi-functionality of the proposed radar.

  • A Dc-coupled biomedical radar sensor with analog Dc Offset calibration circuit
    2018 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), 2018
    Co-Authors: Dongyang Tang, Zhengyu Peng, Yi-chyun Chiang, Jing Wang, Changzhi Li
    Abstract:

    A common problem of biomedical radar sensors is the Dc Offset at the output of radar receiver front-end. In this paper, a Dc-coupled Doppler radar sensor system with an analog Dc Offset calibration circuit is proposed. The calibration circuit can track the change of Dc Offset continuously, and automatically remove the Offset on the fly or in a controlled manner. The proposed calibration circuit uses pure analog components and does not require any digital signal processing (DSP) or software configuration. Compared to existing digitized solutions, the proposed analog calibration technique has the advantage of low cost, low complexity, extremely small delay, and very high resolution. Experiment demonstrates that input signals with a wide range of input Dc Offset can be processed. Hence the dynamic range of the baseband variable gain amplifier (VGA) can be maximized. Furthermore, the proposed Dc Offset calibration architecture can be easily adopted by other systems which also face Dc Offset problem.

  • I2MTC - A Dc-coupled biomedical radar sensor with analog Dc Offset calibration circuit
    2018 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), 2018
    Co-Authors: Dongyang Tang, Zhengyu Peng, Yi-chyun Chiang, Jing Wang, Changzhi Li
    Abstract:

    A common problem of biomedical radar sensors is the Dc Offset at the output of radar receiver front-end. In this paper, a Dc-coupled Doppler radar sensor system with an analog Dc Offset calibration circuit is proposed. The calibration circuit can track the change of Dc Offset continuously, and automatically remove the Offset on the fly or in a controlled manner. The proposed calibration circuit uses pure analog components and does not require any digital signal processing (DSP) or software configuration. Compared to existing digitized solutions, the proposed analog calibration technique has the advantage of low cost, low complexity, extremely small delay, and very high resolution. Experiment demonstrates that input signals with a wide range of input Dc Offset can be processed. Hence the dynamic range of the baseband variable gain amplifier (VGA) can be maximized. Furthermore, the proposed Dc Offset calibration architecture can be easily adopted by other systems which also face Dc Offset problem.

  • Accurate Dc Offset calibration of Doppler radar via non-convex optimisation
    Electronics Letters, 2015
    Co-Authors: Changzhi Li, Feng Xi, Hong Hong, Li Sun, Heng Zhao, Xiaohua Zhu
    Abstract:

    Continuous-wave Doppler radar has attracted a lot of attention for noncontact vital sign detection. In the typical quadrature homotype architecture, the Dc Offset is a tough issue in that it seriously deteriorates the demodulated results. However, existing methods for Dc Offset calibration can hardly obtain accurate compensation, especially when the sparsity of measurement outliers is relatively large. Proposed is a novel iteratively reweighed ℓ1 algorithm-based error correction method. Simulated and experimental results demonstrate the advantages of the method for accurate Dc Offset calibration.