The Experts below are selected from a list of 10863 Experts worldwide ranked by ideXlab platform
Olivier Deforges - One of the best experts on this subject based on the ideXlab platform.
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parallel shvc Decoder Implementation and analysis
International Conference on Multimedia and Expo, 2014Co-Authors: Wassim Hamidouche, M Raulet, Olivier DeforgesAbstract:The new Scalable High efficiency Video Coding (SHVC) standard is based on a multi-loop coding structure which requires the total decoding of all intermediate layers. The decoding complexity becomes then a real issue, especially for a real time decoding of ultra high video resolutions. A parallel processing architecture is proposed to reduce both the decoding time and the latency of the SHVC Decoder. The proposed solution combines the high level parallel processing solutions defined in the HEVC standard with an extension of the frame-based parallelism. The latter solution enables the decoding of several spatial and temporal SHVC frames in parallel to enhance both decoding frame rate and latency. The wavefront parallel processing solution is used for more coarse level of granularity. The proposed hybrid parallel processing approach achieves a near optimal speedup and provides a good trade-off between decoding time, latency and memory usage. On a 6 cores Xeon processor, the parallel SHVC Decoder performs a real time decoding of 1600p60 video resolution.
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ICME - Parallel SHVC Decoder: Implementation and analysis
2014 IEEE International Conference on Multimedia and Expo (ICME), 2014Co-Authors: Wassim Hamidouche, M Raulet, Olivier DeforgesAbstract:The new Scalable High efficiency Video Coding (SHVC) standard is based on a multi-loop coding structure which requires the total decoding of all intermediate layers. The decoding complexity becomes then a real issue, especially for a real time decoding of ultra high video resolutions. A parallel processing architecture is proposed to reduce both the decoding time and the latency of the SHVC Decoder. The proposed solution combines the high level parallel processing solutions defined in the HEVC standard with an extension of the frame-based parallelism. The latter solution enables the decoding of several spatial and temporal SHVC frames in parallel to enhance both decoding frame rate and latency. The wavefront parallel processing solution is used for more coarse level of granularity. The proposed hybrid parallel processing approach achieves a near optimal speedup and provides a good trade-off between decoding time, latency and memory usage. On a 6 cores Xeon processor, the parallel SHVC Decoder performs a real time decoding of 1600p60 video resolution.
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ICIP - Real time SHVC Decoder: Implementation and complexity analysis
2014 IEEE International Conference on Image Processing (ICIP), 2014Co-Authors: Wassim Hamidouche, M Raulet, Olivier DeforgesAbstract:The Scalable High efficiency Video Coding (SHVC) standard is developed to offer spatial and quality scalability with high coding efficiency. In this paper we investigate a complexity analysis of a real time and parallel SHVC Decoder. We first provide details on the Implementation of the SHVC Decoder including its low level optimizations. Furthermore, we introduce parallelism tools integrated in the SHVC software for parallel decoding. These tools include frame-based parallelism to decode a set of temporal and spatial frames in parallel as well as wavefront parallelism to simultaneously process separated regions of a picture. We assessed through experimental results the complexity of the real time SHVC Decoder in different coding configurations. The SHVC Decoder with two layers introduces in average an additional complexity of 43 to 80% in respect to a simulcast configuration. The low level optimizations together with a hybrid parallelism solution enables a real time decoding of 1600p40 enhancement layer on an Intel i7 processor.
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Design of an Embedded Low Complexity Image Coder using CAL language
2009Co-Authors: Khaled Jerbi, Olivier Deforges, Mickael Raulet, Mohamed AbidAbstract:The increasing complexity of image codecs and the time to market requires a high level design. Caltrop Actor Language (CAL) is a domain-specific language that provides useful abstractions for dataflow programming with actor. It has been chosen by the ISO/IEC standardization organization in the new MPEG standard called Reconfigurable Video Coding. This framework is adopted to design a multitude of codecs by combining actors. We present in this paper the specification and synthesis of the image coder LAR (Locally adaptive resolution) using the CAL framework. An HDL description and generation tools are used. The results show that such a high level design is possible. The quality of the resulting Decoder Implementation turns out to be better than that of a VHDL reference design. In the following, the main parts of the LAR coder will be presented; we will introduce the basic notions of the CAL language and its infrastructure (edition, simulation and HDL synthesis tools) and the results will be discussed.
Mohammad M. Mansour - One of the best experts on this subject based on the ideXlab platform.
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a turbo decoding message passing algorithm for sparse parity check matrix codes
IEEE Transactions on Signal Processing, 2006Co-Authors: Mohammad M. MansourAbstract:A turbo-decoding message-passing (TDMP) algorithm for sparse parity-check matrix (SPCM) codes such as low-density parity-check, repeat-accumulate, and turbo-like codes is presented. The main advantages of the proposed algorithm over the standard decoding algorithm are 1) its faster convergence speed by a factor of two in terms of decoding iterations, 2) improvement in coding gain by an order of magnitude at high signal-to-noise ratio (SNR), 3) reduced memory requirements, and 4) reduced Decoder complexity. In addition, an efficient algorithm for message computation using simple "max" operations is also presented. Analysis using EXIT charts shows that the TDMP algorithm offers a better performance-complexity tradeoff when the number of decoding iterations is small, which is attractive for high-speed applications. A parallel version of the TDMP algorithm in conjunction with architecture-aware (AA) SPCM codes, which have embedded structure that enables efficient high-throughput Decoder Implementation, are presented. Design examples of AA-SPCM codes based on graphs with large girth demonstrate that AA-SPCM codes have very good error-correcting capability using the TDMP algorithm
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VLSI Design for High-Speed Sparse Parity-Check Matrix Decoders
Conference Record of the Thirty-Ninth Asilomar Conference onSignals Systems and Computers 2005., 1Co-Authors: Mohammad M. MansourAbstract:In this paper, the design of high-speed iterative Decoders for sparse parity-check matrix (SPCM) codes such as LDPC, repeat-accumulate and turbo-like codes is addressed. The random nature of the underlying Tanner graph associated with these codes is problematic for a high-speed Decoder Implementation. This issue is addressed by designing structured SPCM codes tailored for low-complexity scalable Decoders using the turbo-decoding message-passing (TDMP) algorithm. Analysis using EXIT charts shows that a better performance/complexity tradeoff is achieved when the number of decoding iterations is small which is attractive for high-speed applications. A scalable Decoder architecture for structures SPCM codes employing the TDMP algorithm is presented
Wassim Hamidouche - One of the best experts on this subject based on the ideXlab platform.
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parallel shvc Decoder Implementation and analysis
International Conference on Multimedia and Expo, 2014Co-Authors: Wassim Hamidouche, M Raulet, Olivier DeforgesAbstract:The new Scalable High efficiency Video Coding (SHVC) standard is based on a multi-loop coding structure which requires the total decoding of all intermediate layers. The decoding complexity becomes then a real issue, especially for a real time decoding of ultra high video resolutions. A parallel processing architecture is proposed to reduce both the decoding time and the latency of the SHVC Decoder. The proposed solution combines the high level parallel processing solutions defined in the HEVC standard with an extension of the frame-based parallelism. The latter solution enables the decoding of several spatial and temporal SHVC frames in parallel to enhance both decoding frame rate and latency. The wavefront parallel processing solution is used for more coarse level of granularity. The proposed hybrid parallel processing approach achieves a near optimal speedup and provides a good trade-off between decoding time, latency and memory usage. On a 6 cores Xeon processor, the parallel SHVC Decoder performs a real time decoding of 1600p60 video resolution.
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ICME - Parallel SHVC Decoder: Implementation and analysis
2014 IEEE International Conference on Multimedia and Expo (ICME), 2014Co-Authors: Wassim Hamidouche, M Raulet, Olivier DeforgesAbstract:The new Scalable High efficiency Video Coding (SHVC) standard is based on a multi-loop coding structure which requires the total decoding of all intermediate layers. The decoding complexity becomes then a real issue, especially for a real time decoding of ultra high video resolutions. A parallel processing architecture is proposed to reduce both the decoding time and the latency of the SHVC Decoder. The proposed solution combines the high level parallel processing solutions defined in the HEVC standard with an extension of the frame-based parallelism. The latter solution enables the decoding of several spatial and temporal SHVC frames in parallel to enhance both decoding frame rate and latency. The wavefront parallel processing solution is used for more coarse level of granularity. The proposed hybrid parallel processing approach achieves a near optimal speedup and provides a good trade-off between decoding time, latency and memory usage. On a 6 cores Xeon processor, the parallel SHVC Decoder performs a real time decoding of 1600p60 video resolution.
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ICIP - Real time SHVC Decoder: Implementation and complexity analysis
2014 IEEE International Conference on Image Processing (ICIP), 2014Co-Authors: Wassim Hamidouche, M Raulet, Olivier DeforgesAbstract:The Scalable High efficiency Video Coding (SHVC) standard is developed to offer spatial and quality scalability with high coding efficiency. In this paper we investigate a complexity analysis of a real time and parallel SHVC Decoder. We first provide details on the Implementation of the SHVC Decoder including its low level optimizations. Furthermore, we introduce parallelism tools integrated in the SHVC software for parallel decoding. These tools include frame-based parallelism to decode a set of temporal and spatial frames in parallel as well as wavefront parallelism to simultaneously process separated regions of a picture. We assessed through experimental results the complexity of the real time SHVC Decoder in different coding configurations. The SHVC Decoder with two layers introduces in average an additional complexity of 43 to 80% in respect to a simulcast configuration. The low level optimizations together with a hybrid parallelism solution enables a real time decoding of 1600p40 enhancement layer on an Intel i7 processor.
Chiying Tsui - One of the best experts on this subject based on the ideXlab platform.
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an efficient partial sum network architecture for semi parallel polar codes Decoder Implementation
IEEE Transactions on Signal Processing, 2014Co-Authors: Youzhe Fan, Chiying TsuiAbstract:Polar codes have recently received a lot of attention because of their capacity-achieving performance and low encoding and decoding complexity. The performance of the successive cancellation Decoder (SCD) of the polar codes highly depends on that of the partial-sum network (PSN) Implementation. Hence, in this work, an efficient PSN architecture is proposed, based on the properties of polar codes. First, a new partial-sum updating algorithm and the corresponding PSN architecture are introduced which achieve a delay performance independent of the code length. Moreover, the area complexity is also reduced. Second, for a high-performance and area-efficient semi-parallel SCD Implementation, a folded PSN architecture is presented to integrate seamlessly with the folded processing element architecture. This is achieved by using a novel folded decoding schedule. As a result, both the critical path delay and the area (excluding the memory for folding) of the semi-parallel SCD are approximately constant for a large range of code lengths. The proposed designs are implemented in both FPGA and ASIC and compared with the existing designs. Experimental result shows that for polar codes with large code length, the decoding throughput is improved by more than 1.05 times and the area is reduced by as much as 50.4%, compared with the state-of-the-art designs.
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low power limited search parallel state viterbi Decoder Implementation based on scarce state transition
IEEE Transactions on Very Large Scale Integration Systems, 2007Co-Authors: Jie Jin, Chiying TsuiAbstract:In this paper, a low-power Viterbi Decoder design based on scarce state transition (SST) is presented. A low complexity algorithm based on a limited search algorithm, which reduces the average number of the add-compare-select computation of the Viterbi algorithm, is proposed and seamlessly integrated with the SST-based Decoder. The new decoding scheme has low overhead and facilitates low-power Implementation for high throughput applications. We also propose an uneven-partitioned memory architecture for the trace-back survivor memory unit to reduce the overall memory access power. The new Viterbi Decoder is designed and implemented in TSMC 0.18-mum CMOS process. Simulation results show that power consumption is reduced by up to 80% for high throughput wireless systems such as Multiband-OFDM Ultra-wideband applications.
M Raulet - One of the best experts on this subject based on the ideXlab platform.
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parallel shvc Decoder Implementation and analysis
International Conference on Multimedia and Expo, 2014Co-Authors: Wassim Hamidouche, M Raulet, Olivier DeforgesAbstract:The new Scalable High efficiency Video Coding (SHVC) standard is based on a multi-loop coding structure which requires the total decoding of all intermediate layers. The decoding complexity becomes then a real issue, especially for a real time decoding of ultra high video resolutions. A parallel processing architecture is proposed to reduce both the decoding time and the latency of the SHVC Decoder. The proposed solution combines the high level parallel processing solutions defined in the HEVC standard with an extension of the frame-based parallelism. The latter solution enables the decoding of several spatial and temporal SHVC frames in parallel to enhance both decoding frame rate and latency. The wavefront parallel processing solution is used for more coarse level of granularity. The proposed hybrid parallel processing approach achieves a near optimal speedup and provides a good trade-off between decoding time, latency and memory usage. On a 6 cores Xeon processor, the parallel SHVC Decoder performs a real time decoding of 1600p60 video resolution.
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ICME - Parallel SHVC Decoder: Implementation and analysis
2014 IEEE International Conference on Multimedia and Expo (ICME), 2014Co-Authors: Wassim Hamidouche, M Raulet, Olivier DeforgesAbstract:The new Scalable High efficiency Video Coding (SHVC) standard is based on a multi-loop coding structure which requires the total decoding of all intermediate layers. The decoding complexity becomes then a real issue, especially for a real time decoding of ultra high video resolutions. A parallel processing architecture is proposed to reduce both the decoding time and the latency of the SHVC Decoder. The proposed solution combines the high level parallel processing solutions defined in the HEVC standard with an extension of the frame-based parallelism. The latter solution enables the decoding of several spatial and temporal SHVC frames in parallel to enhance both decoding frame rate and latency. The wavefront parallel processing solution is used for more coarse level of granularity. The proposed hybrid parallel processing approach achieves a near optimal speedup and provides a good trade-off between decoding time, latency and memory usage. On a 6 cores Xeon processor, the parallel SHVC Decoder performs a real time decoding of 1600p60 video resolution.
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ICIP - Real time SHVC Decoder: Implementation and complexity analysis
2014 IEEE International Conference on Image Processing (ICIP), 2014Co-Authors: Wassim Hamidouche, M Raulet, Olivier DeforgesAbstract:The Scalable High efficiency Video Coding (SHVC) standard is developed to offer spatial and quality scalability with high coding efficiency. In this paper we investigate a complexity analysis of a real time and parallel SHVC Decoder. We first provide details on the Implementation of the SHVC Decoder including its low level optimizations. Furthermore, we introduce parallelism tools integrated in the SHVC software for parallel decoding. These tools include frame-based parallelism to decode a set of temporal and spatial frames in parallel as well as wavefront parallelism to simultaneously process separated regions of a picture. We assessed through experimental results the complexity of the real time SHVC Decoder in different coding configurations. The SHVC Decoder with two layers introduces in average an additional complexity of 43 to 80% in respect to a simulcast configuration. The low level optimizations together with a hybrid parallelism solution enables a real time decoding of 1600p40 enhancement layer on an Intel i7 processor.
