The Experts below are selected from a list of 681 Experts worldwide ranked by ideXlab platform
David Wentzlaff - One of the best experts on this subject based on the ideXlab platform.
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FPGA - JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores
Proceedings of the 2019 ACM SIGDA International Symposium on Field-Programmable Gate Arrays, 2019Co-Authors: Katie Lim, Jonathan Balkind, David WentzlaffAbstract:Energy efficiency has become an increasingly important concern in computer architecture due to the end of Dennard Scaling. Heterogeneity has been explored as a way to achieve better energy efficiency and heterogeneous microarchitecture chips have become common in the mobile setting. Recent research has explored using heterogeneous-ISA, heterogeneous microarchitecture, general-purpose cores to achieve further energy efficiency gains. However, there is no open-source hardware implementation of a heterogeneous-ISA processor available for research, and effective research on heterogeneous-ISA processors necessitates the emulation speed provided by FPGA prototyping. This work describes our experiences creating JuxtaPiton by integrating a small RISC-V core into the OpenPiton framework, which uses a modified OpenSPARC T1 core. This is the first time a new core has been integrated with the OpenPiton framework, and JuxtaPiton is the first open-source, general-purpose, heterogeneous-ISA processor. JuxtaPiton inherits all the capabilities of OpenPiton, including vital FPGA emulation infrastructure which can boot full-stack Debian Linux. Using this infrastructure, we investigate area and timing effects of using the new RISC-V core on FPGA and the performance of the new core running microbenchmarks.
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JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores
arXiv: Hardware Architecture, 2018Co-Authors: Katie Lim, Jonathan Balkind, David WentzlaffAbstract:Energy efficiency has become an increasingly important concern in computer architecture due to the end of Dennard Scaling. Heterogeneity has been explored as a way to achieve better energy efficiency and heterogeneous microarchitecture chips have become common in the mobile setting. Recent research has explored using heterogeneous-ISA, heterogeneous microarchitecture, general-purpose cores to achieve further energy efficiency gains. However, there is no open-source hardware implementation of a heterogeneous-ISA processor available for research, and effective research on heterogeneous-ISA processors necessitates the emulation speed provided by FPGA prototyping. This work describes our experiences creating JuxtaPiton by integrating a small RISC-V core into the OpenPiton framework, which uses a modified OpenSPARC T1 core. This is the first time a new core has been integrated with the OpenPiton framework, and JuxtaPiton is the first open-source, general-purpose, heterogeneous-ISA processor. JuxtaPiton inherits all the capabilities of OpenPiton, including vital FPGA emulation infrastructure which can boot full-stack Debian Linux. Using this infrastructure, we investigate area and timing effects of using the new RISC-V core on FPGA and the performance of the new core running microbenchmarks.
Yong Chen - One of the best experts on this subject based on the ideXlab platform.
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opensoc system architect an open toolkit for building soft cores on fpgas
Field-Programmable Logic and Applications, 2017Co-Authors: Farzad Fatollahifard, David Donofrio, John Leidel, John Shalf, Xi Wang, Yong ChenAbstract:Given the recent difficulty in continuing the classic CMOS manufacturing density and power Scaling curves, also known as Moore's Law and Dennard Scaling, respectively, we find that modern complex system architectures are increasingly relying upon accelerators in order to optimize the placement of specific computational workloads. In addition, large-scale computing infrastructures utilized in HPC, data intensive computing, and cloud computing must rely almost exclusively upon commodity device architectures provided by third-party manufacturers. The end result being a final system architecture that lacks specificity for the target software workload. At the same time, there is a trend in the FPGA space of much larger FPGAs with a lot more resources and hardened IP blocks, making this type of architecture design space exploration much easier. The OpenSoC System Architect infrastructure combines several open source design tools and methodologies into a central infrastructure for designing, developing, and verifying the necessary hardware and software modules required to implement application-specific processors for use in FPGAs. The end result is an infrastructure that permits rapid development and deployment of application-specific accelerators and softcores, including a fully functional software development tool chain.
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FPL - OpenSoC system architect: An open toolkit for building soft-cores on FPGAs
2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017Co-Authors: Farzad Fatollahi-fard, David Donofrio, John Leidel, John Shalf, Xi Wang, Yong ChenAbstract:Given the recent difficulty in continuing the classic CMOS manufacturing density and power Scaling curves, also known as Moore's Law and Dennard Scaling, respectively, we find that modern complex system architectures are increasingly relying upon accelerators in order to optimize the placement of specific computational workloads. In addition, large-scale computing infrastructures utilized in HPC, data intensive computing, and cloud computing must rely almost exclusively upon commodity device architectures provided by third-party manufacturers. The end result being a final system architecture that lacks specificity for the target software workload. At the same time, there is a trend in the FPGA space of much larger FPGAs with a lot more resources and hardened IP blocks, making this type of architecture design space exploration much easier. The OpenSoC System Architect infrastructure combines several open source design tools and methodologies into a central infrastructure for designing, developing, and verifying the necessary hardware and software modules required to implement application-specific processors for use in FPGAs. The end result is an infrastructure that permits rapid development and deployment of application-specific accelerators and softcores, including a fully functional software development tool chain.
Murali Annavaram - One of the best experts on this subject based on the ideXlab platform.
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HPCA - Approximating warps with intra-warp operand value similarity
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016Co-Authors: Daniel Wong, Nam Sung Kim, Murali AnnavaramAbstract:Value locality, the recurrence of a previously-seen value, has been the enabler of myriad optimization techniques in traditional processors. Value similarity relaxes the constraint of value locality by allowing values to differ in the lowest significant bits where values are micro-architecturally near. With the end of Dennard Scaling and the turn towards massively parallel accelerators, we revisit value similarity in the context of GPUs. We identify a form of value similarity called intra-warp operand value similarity, which is abundant in GPUs. We present Warp Approximation, which leverages intra-warp operand value similarity to trade off accuracy for energy. Warp Approximation dynamically identifies intra-warp operand value similarity in hardware, and executes a single representative thread on behalf of all the active threads in a warp, thereby producing a representative value with approximate value locality. This representative value can then be stored compactly in the register file as a value similar scalar, reducing the read and write energy when dealing with approximate data. With Warp Approximation, we can reduce execution unit energy by 37%, register file energy by 28%, and improve overall GPGPU energy efficiency by 26% with minimal quality degradation.
Katie Lim - One of the best experts on this subject based on the ideXlab platform.
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FPGA - JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores
Proceedings of the 2019 ACM SIGDA International Symposium on Field-Programmable Gate Arrays, 2019Co-Authors: Katie Lim, Jonathan Balkind, David WentzlaffAbstract:Energy efficiency has become an increasingly important concern in computer architecture due to the end of Dennard Scaling. Heterogeneity has been explored as a way to achieve better energy efficiency and heterogeneous microarchitecture chips have become common in the mobile setting. Recent research has explored using heterogeneous-ISA, heterogeneous microarchitecture, general-purpose cores to achieve further energy efficiency gains. However, there is no open-source hardware implementation of a heterogeneous-ISA processor available for research, and effective research on heterogeneous-ISA processors necessitates the emulation speed provided by FPGA prototyping. This work describes our experiences creating JuxtaPiton by integrating a small RISC-V core into the OpenPiton framework, which uses a modified OpenSPARC T1 core. This is the first time a new core has been integrated with the OpenPiton framework, and JuxtaPiton is the first open-source, general-purpose, heterogeneous-ISA processor. JuxtaPiton inherits all the capabilities of OpenPiton, including vital FPGA emulation infrastructure which can boot full-stack Debian Linux. Using this infrastructure, we investigate area and timing effects of using the new RISC-V core on FPGA and the performance of the new core running microbenchmarks.
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JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores
arXiv: Hardware Architecture, 2018Co-Authors: Katie Lim, Jonathan Balkind, David WentzlaffAbstract:Energy efficiency has become an increasingly important concern in computer architecture due to the end of Dennard Scaling. Heterogeneity has been explored as a way to achieve better energy efficiency and heterogeneous microarchitecture chips have become common in the mobile setting. Recent research has explored using heterogeneous-ISA, heterogeneous microarchitecture, general-purpose cores to achieve further energy efficiency gains. However, there is no open-source hardware implementation of a heterogeneous-ISA processor available for research, and effective research on heterogeneous-ISA processors necessitates the emulation speed provided by FPGA prototyping. This work describes our experiences creating JuxtaPiton by integrating a small RISC-V core into the OpenPiton framework, which uses a modified OpenSPARC T1 core. This is the first time a new core has been integrated with the OpenPiton framework, and JuxtaPiton is the first open-source, general-purpose, heterogeneous-ISA processor. JuxtaPiton inherits all the capabilities of OpenPiton, including vital FPGA emulation infrastructure which can boot full-stack Debian Linux. Using this infrastructure, we investigate area and timing effects of using the new RISC-V core on FPGA and the performance of the new core running microbenchmarks.
Mingoo Seok - One of the best experts on this subject based on the ideXlab platform.
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master of none acceleration a comparison of accelerator architectures for analytical query processing
International Symposium on Computer Architecture, 2019Co-Authors: Andrea Lottarini, Joao P Cerqueira, Thomas J Repetti, Stephen A Edwards, Kenneth A Ross, Mingoo SeokAbstract:Hardware accelerators are one promising solution to contend with the end of Dennard Scaling and the slowdown of Moore's law. For mature workloads that are regular and have high compute per byte, hardening an application into one or more hardware modules is a standard approach. However, for some applications, we find that a programmable homogeneous architecture is preferable. This paper compares a previously proposed heterogeneous hardware accelerator for analytical query processing to a homogeneous systolic array alternative. We find that the heterogeneous and homogeneous accelerators are equivalent for large designs, while for small designs the homogeneous is better. Our analysis explains this counter-intuitive result, finding that the homogeneous architecture has higher average resource utilization and lower relative costs for the communication infrastructure.
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ISCA - Master of none acceleration: a comparison of accelerator architectures for analytical query processing
Proceedings of the 46th International Symposium on Computer Architecture, 2019Co-Authors: Andrea Lottarini, Joao P Cerqueira, Thomas J Repetti, Stephen A Edwards, Kenneth A Ross, Mingoo Seok, Martha A. KimAbstract:Hardware accelerators are one promising solution to contend with the end of Dennard Scaling and the slowdown of Moore's law. For mature workloads that are regular and have high compute per byte, hardening an application into one or more hardware modules is a standard approach. However, for some applications, we find that a programmable homogeneous architecture is preferable. This paper compares a previously proposed heterogeneous hardware accelerator for analytical query processing to a homogeneous systolic array alternative. We find that the heterogeneous and homogeneous accelerators are equivalent for large designs, while for small designs the homogeneous is better. Our analysis explains this counter-intuitive result, finding that the homogeneous architecture has higher average resource utilization and lower relative costs for the communication infrastructure.