The Experts below are selected from a list of 50052 Experts worldwide ranked by ideXlab platform
Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.
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Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems
Journal of Signal Processing Systems, 2012Co-Authors: Georgios Karakonstantis, Debabrata Mohapatra, Kaushik RoyAbstract:In this paper, we propose a system level Design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing “just-the-right” amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the “less- crucial” computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system–logic and memory–and spans multiple layers of Design Hierarchy–algorithm, architecture and circuit. The Design methodology when applied to a multimedia sub-system shows large power benefits (up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.
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an alternate Design paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design Hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
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ASP-DAC - An alternate Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design Hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
Patrick Ndai - One of the best experts on this subject based on the ideXlab platform.
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an alternate Design paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design Hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
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ASP-DAC - An alternate Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design Hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
Ashish Goel - One of the best experts on this subject based on the ideXlab platform.
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an alternate Design paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design Hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
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ASP-DAC - An alternate Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design Hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
Haixin Liu - One of the best experts on this subject based on the ideXlab platform.
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an alternate Design paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design Hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
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ASP-DAC - An alternate Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design Hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
Wen-jong Fang - One of the best experts on this subject based on the ideXlab platform.
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Multiway FPGA partitioning by fully exploiting Design Hierarchy
ACM Transactions on Design Automation of Electronic Systems, 2000Co-Authors: Wen-jong FangAbstract:In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the Design Hierarchy. We propose a novel multiple-FPGA synthesis and partitioning method which is performed in three phases: (1) fine-grained synthesis, (2) functional-based clustering, and (3) hierarchical set-covering partitioning. This method first synthesizes a Design specification in a fine-grained way so that functional clusters can be preserved based on the structural nature of the Design specification. Then, it applies a hierarchical set-covering partitioning method to form the final FPGA partitions. Experimental results on a number of benchmarks and industrial Designs demonstrate that IsO limits are the bottleneck for CLB utilization when applying a traditional multiple-FPGA synthesis method on flattened netlists. In contrast, by fully exploiting the Design structural Hierarchy during the multiple-FPGA partitioning, our proposed method produces fewer FPGA partitions with higher CLB and lower IsO-pin utilizations.
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DAC - Multi-way FPGA partitioning by fully exploiting Design Hierarchy
Proceedings of the 34th annual conference on Design automation conference - DAC '97, 1997Co-Authors: Wen-jong FangAbstract:In this paper, we present a new integrated synthesisand partitioning method for multiple-FPGA applications.This method first synthesizes a Design specificationin a fine-grained way so that functional clusters can bepreserved based on the structural nature of the Designspecification.Then, it applies a hierarchical set-coveringpartitioning method to form the final FPGA partitionings.Our approach bridges the gap between HDL synthesisand physical partitioning by fully exploiting the DesignHierarchy.Experimental results on a number of benchmarksand industrial Designs demonstrate that I/O limitsare the bottleneck for CLB utilization when applying atraditional multiple-FPGA synthesis method on flattenednetlists.In contrast, by fully exploiting the Design structuralHierarchy during the multiple-FPGA partitioning,our proposed method produces fewer FPGA partitionswith higher CLB and low I/O-pin utilizations.