The Experts below are selected from a list of 143919 Experts worldwide ranked by ideXlab platform
Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.
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Design Paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
IEEE Transactions on Very Large Scale Integration Systems, 2010Co-Authors: Jing Li, Patrick Ndai, Sayeef Salahuddin, Ashish Goel, Kaushik RoyAbstract:Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient Design Paradigm from circuit and/or architecture perspective-to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting Design requirements for read stability, writability and cell area. It can be used at an early stage of the Design cycle for yield enhancement.
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Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010Co-Authors: Patrick Ndai, Sayeef Salahuddin, Ashish Goel, Kaushik RoyAbstract:Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient Design Paradigm from circuit and/or architecture perspective-to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting Design requirements for read stability, writability and cell area. It can be used at an early stage of the Design cycle for yield enhancement.
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an alternate Design Paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design Paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
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ASP-DAC - An alternate Design Paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design Paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
Patrick Ndai - One of the best experts on this subject based on the ideXlab platform.
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Design Paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
IEEE Transactions on Very Large Scale Integration Systems, 2010Co-Authors: Jing Li, Patrick Ndai, Sayeef Salahuddin, Ashish Goel, Kaushik RoyAbstract:Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient Design Paradigm from circuit and/or architecture perspective-to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting Design requirements for read stability, writability and cell area. It can be used at an early stage of the Design cycle for yield enhancement.
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Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010Co-Authors: Patrick Ndai, Sayeef Salahuddin, Ashish Goel, Kaushik RoyAbstract:Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient Design Paradigm from circuit and/or architecture perspective-to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting Design requirements for read stability, writability and cell area. It can be used at an early stage of the Design cycle for yield enhancement.
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an alternate Design Paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design Paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
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ASP-DAC - An alternate Design Paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design Paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
Ashish Goel - One of the best experts on this subject based on the ideXlab platform.
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Design Paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
IEEE Transactions on Very Large Scale Integration Systems, 2010Co-Authors: Jing Li, Patrick Ndai, Sayeef Salahuddin, Ashish Goel, Kaushik RoyAbstract:Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient Design Paradigm from circuit and/or architecture perspective-to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting Design requirements for read stability, writability and cell area. It can be used at an early stage of the Design cycle for yield enhancement.
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Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010Co-Authors: Patrick Ndai, Sayeef Salahuddin, Ashish Goel, Kaushik RoyAbstract:Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient Design Paradigm from circuit and/or architecture perspective-to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting Design requirements for read stability, writability and cell area. It can be used at an early stage of the Design cycle for yield enhancement.
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an alternate Design Paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design Paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
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ASP-DAC - An alternate Design Paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design Paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
Abeer Samy Yousef Mohamed - One of the best experts on this subject based on the ideXlab platform.
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Smart Materials Innovative Technologies in architecture; Towards Innovative Design Paradigm
Energy Procedia, 2017Co-Authors: Abeer Samy Yousef MohamedAbstract:Smart materials technologies are the key to 21st-century competitive advantage. Various building materials can significantly increase levels of functionality. "Smart Materials" will play critical role in building technology development; these materials that form part of a smart structural system, which has the capability to sense its environment, so smart materials can perform like living systems. Recognizing that the traditional partition between Materials Science and Architecture is obsolete, the study intent is to show how these two fields are intrinsically connected while growing ever more symbiotic as we progress into the future. The paper provides an analytical study of the types of smart materials available, giving a new insight into innovative methods and techniques that will give a new inspiration for architectural Design, which the study will introduce "A New Innovative Design Paradigm".
Haixin Liu - One of the best experts on this subject based on the ideXlab platform.
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an alternate Design Paradigm for robust spin torque transfer magnetic ram stt mram from circuit architecture perspective
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design Paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).
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ASP-DAC - An alternate Design Paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik RoyAbstract:Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of Design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate Design Paradigm ---circuit/architecture co-Design --- to take advantage of different levels of Design hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting Design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%).