The Experts below are selected from a list of 67833 Experts worldwide ranked by ideXlab platform
J.c. López - One of the best experts on this subject based on the ideXlab platform.
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The Design Space layer: supporting early Design Space exploration for core-based Designs
Design Automation and Test in Europe Conference and Exhibition 1999. Proceedings (Cat. No. PR00078), 1999Co-Authors: H.p. Peixoto, M.f. Jacome, A Royo, J.c. LópezAbstract:A novel library layer, called the "Design Space layer," is proposed, aimed at supporting both IP-based and traditional "in-house" Design methodologies, during early Design Space exploration. Strategies for effectively pruning the large Design Spaces characteristic of system-on-a-chip Designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is self-documented and highly compartmentalized into hierarchies of classes of Design objects, and is thus easily scalable. A Design Space layer developed for encryption applications is presented and discussed in some detail.
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Evaluation of Design Space exploration strategies
Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium, 1999Co-Authors: Francisco Moya, José M. Moya, J.c. LópezAbstract:The Design Space exploration (DSE) subsystem of a Design automation tool is responsible for early identification of interesting zones of the Design Space. Evaluation of the exploration strategy used in a tool is extremely difficult because there is not enough information about either the Design Space or the actual cost function. This paper describes a software environment for quantitative evaluation of isolated exploration algorithms based on a completely simulated framework. A simple model of the Design Space allows easy representation of interesting properties of exploration algorithms.
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EUROMICRO - Evaluation of Design Space exploration strategies
Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium, 1999Co-Authors: Francisco Moya, José M. Moya, J.c. LópezAbstract:The Design Space exploration (DSE) subsystem of a Design automation tool is responsible for early identification of interesting zones of the Design Space. Evaluation of the exploration strategy used in a tool is extremely difficult because there is not enough information about either the Design Space or the actual cost function. This paper describes a software environment for quantitative evaluation of isolated exploration algorithms based on a completely simulated framework. A simple model of the Design Space allows easy representation of interesting properties of exploration algorithms.
Andy D. Pimentel - One of the best experts on this subject based on the ideXlab platform.
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Design Space pruning through hybrid analysis in system-level Design Space exploration
2012 Design Automation & Test in Europe Conference & Exhibition (DATE), 2012Co-Authors: Roberta Piscitelli, Andy D. PimentelAbstract:System-level Design Space exploration (DSE), which is performed early in the Design process, is of eminent importance to the Design of complex multi-processor embedded system architectures. During system-level DSE, system parameters like, e.g., the number and type of processors, the type and size of memories, or the mapping of application tasks to architectural resources, are considered. Simulation-based DSE, in which different Design instances are evaluated using system-level simulations, typically are computationally costly. Even using high-level simulations and efficient exploration algorithms, the simulation time to evaluate Design points forms a real bottleneck in such DSE. Therefore, the vast Design Space that needs to be searched requires effective Design Space pruning techniques. This paper presents a technique to reduce the number of simulations needed during system-level DSE. More specifically, we propose an iterative Design Space pruning methodology based on static throughput analysis of different application mappings. By interleaving these analytical throughput estimations with simulations, our hybrid approach can significantly reduce the number of simulations that are needed during the process of DSE.
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DATE - Design Space pruning through hybrid analysis in system-level Design Space exploration
2012 Design Automation & Test in Europe Conference & Exhibition (DATE), 2012Co-Authors: Roberta Piscitelli, Andy D. PimentelAbstract:System-level Design Space exploration (DSE), which is performed early in the Design process, is of eminent importance to the Design of complex multi-processor embedded system architectures. During system-level DSE, system parameters like, e.g., the number and type of processors, the type and size of memories, or the mapping of application tasks to architectural resources, are considered. Simulation-based DSE, in which different Design instances are evaluated using system-level simulations, typically are computationally costly. Even using high-level simulations and efficient exploration algorithms, the simulation time to evaluate Design points forms a real bottleneck in such DSE. Therefore, the vast Design Space that needs to be searched requires effective Design Space pruning techniques. This paper presents a technique to reduce the number of simulations needed during system-level DSE. More specifically, we propose an iterative Design Space pruning methodology based on static throughput analysis of different application mappings. By interleaving these analytical throughput estimations with simulations, our hybrid approach can significantly reduce the number of simulations that are needed during the process of DSE.
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Visualization of Multi-objective Design Space Exploration for Embedded Systems
2010 13th Euromicro Conference on Digital System Design: Architectures Methods and Tools, 2010Co-Authors: Toktam Taghavi, Andy D. PimentelAbstract:Modern embedded systems come with contradictory Design constraints. On one hand, these systems often target mass production and battery-based devices, and therefore should be cheap and power efficient. On the other hand, they need to achieve high (real-time) performance. This wide spectrum of Design requirements leads to complex heterogeneous system-on-chip (SoC) architectures. The complexity of embedded systems forces Designers to model and simulate systems and their components to explore the wide range of Design choices. Such Design Space exploration is especially needed during the early Design stages, where the Design Space is at its largest. Due to the exponential Design Space in real problems and multiple criteria to be considered, multi-objective evolutionary algorithms (MOEAs) are often used to trim down a large Design Space into a finite set of points and provide the Designer a set of tradable solutions with respect to the Design criteria. Interpreting the search results (e.g., where are the Pareto points located), understanding their relations and analyzing how the Design Space was searched by such searching algorithms is of invaluable importance to the Designer. To this end, this paper presents a novel interactive visualization tool, based on tree visualization, to understand the search dynamics of a MOEA and to visualize where the optimum Design points are located in the Design Space and what objective values they have.
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System-level MP-SoC Design Space exploration using tree visualization
2009 IEEE ACM IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia, 2009Co-Authors: Toktam Taghavi, Andy D. Pimentel, Mark ThompsonAbstract:The complexity of today's embedded systems forces Designers to model and simulate systems and their components to explore the wide range of Design choices. Such Design Space exploration is especially needed during the early Design stages, where the Design Space is at its largest. Due to the exponential Design Space in real problems, evaluating and comparing every single point in the Design Space is infeasible. Therefore, heuristic search techniques, such as Evolutionary Algorithms (EA), are often used to search the Design Space for optimum Design points using only a finite number of Design-point evaluations. Understanding how the Design Space was searched by such searching algorithms and providing insight into the ¿landscape¿ of the Design Space, may be of invaluable importance to the Designer, To this end, this paper presents a novel interactive visualization application, based on tree visualization, to understand the search dynamics of an evolutionary algorithm and to visualize where the optimum Design points are located in the Design Space.
H.p. Peixoto - One of the best experts on this subject based on the ideXlab platform.
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DATE - The Design Space layer: supporting early Design Space exploration for core-based Designs
Proceedings of the conference on Design automation and test in Europe - DATE '99, 1999Co-Authors: H.p. Peixoto, M.f. Jacome, A Royo, Juan Carlos LópezAbstract:A novel library layer, called the "Design Space layer," is proposed, aimed at supporting both IP-based and traditional "in-house" Design methodologies, during early Design Space exploration. Strategies for effectively pruning the large Design Spaces characteristic of system-on-a-chip Designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is self-documented and highly compartmentalized into hierarchies of classes of Design objects, and is thus easily scalable. A Design Space layer developed for encryption applications is presented and discussed in some detail.
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The Design Space layer: supporting early Design Space exploration for core-based Designs
Design Automation and Test in Europe Conference and Exhibition 1999. Proceedings (Cat. No. PR00078), 1999Co-Authors: H.p. Peixoto, M.f. Jacome, A Royo, J.c. LópezAbstract:A novel library layer, called the "Design Space layer," is proposed, aimed at supporting both IP-based and traditional "in-house" Design methodologies, during early Design Space exploration. Strategies for effectively pruning the large Design Spaces characteristic of system-on-a-chip Designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is self-documented and highly compartmentalized into hierarchies of classes of Design objects, and is thus easily scalable. A Design Space layer developed for encryption applications is presented and discussed in some detail.
A Royo - One of the best experts on this subject based on the ideXlab platform.
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DATE - The Design Space layer: supporting early Design Space exploration for core-based Designs
Proceedings of the conference on Design automation and test in Europe - DATE '99, 1999Co-Authors: H.p. Peixoto, M.f. Jacome, A Royo, Juan Carlos LópezAbstract:A novel library layer, called the "Design Space layer," is proposed, aimed at supporting both IP-based and traditional "in-house" Design methodologies, during early Design Space exploration. Strategies for effectively pruning the large Design Spaces characteristic of system-on-a-chip Designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is self-documented and highly compartmentalized into hierarchies of classes of Design objects, and is thus easily scalable. A Design Space layer developed for encryption applications is presented and discussed in some detail.
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The Design Space layer: supporting early Design Space exploration for core-based Designs
Design Automation and Test in Europe Conference and Exhibition 1999. Proceedings (Cat. No. PR00078), 1999Co-Authors: H.p. Peixoto, M.f. Jacome, A Royo, J.c. LópezAbstract:A novel library layer, called the "Design Space layer," is proposed, aimed at supporting both IP-based and traditional "in-house" Design methodologies, during early Design Space exploration. Strategies for effectively pruning the large Design Spaces characteristic of system-on-a-chip Designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is self-documented and highly compartmentalized into hierarchies of classes of Design objects, and is thus easily scalable. A Design Space layer developed for encryption applications is presented and discussed in some detail.
M.f. Jacome - One of the best experts on this subject based on the ideXlab platform.
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DATE - The Design Space layer: supporting early Design Space exploration for core-based Designs
Proceedings of the conference on Design automation and test in Europe - DATE '99, 1999Co-Authors: H.p. Peixoto, M.f. Jacome, A Royo, Juan Carlos LópezAbstract:A novel library layer, called the "Design Space layer," is proposed, aimed at supporting both IP-based and traditional "in-house" Design methodologies, during early Design Space exploration. Strategies for effectively pruning the large Design Spaces characteristic of system-on-a-chip Designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is self-documented and highly compartmentalized into hierarchies of classes of Design objects, and is thus easily scalable. A Design Space layer developed for encryption applications is presented and discussed in some detail.
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The Design Space layer: supporting early Design Space exploration for core-based Designs
Design Automation and Test in Europe Conference and Exhibition 1999. Proceedings (Cat. No. PR00078), 1999Co-Authors: H.p. Peixoto, M.f. Jacome, A Royo, J.c. LópezAbstract:A novel library layer, called the "Design Space layer," is proposed, aimed at supporting both IP-based and traditional "in-house" Design methodologies, during early Design Space exploration. Strategies for effectively pruning the large Design Spaces characteristic of system-on-a-chip Designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is self-documented and highly compartmentalized into hierarchies of classes of Design objects, and is thus easily scalable. A Design Space layer developed for encryption applications is presented and discussed in some detail.