The Experts below are selected from a list of 1743 Experts worldwide ranked by ideXlab platform
Ygal Arbel - One of the best experts on this subject based on the ideXlab platform.
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FPGA - Network-on-Chip Programmable Platform in Versal TM ACAP Architecture
Proceedings of the 2019 ACM SIGDA International Symposium on Field-Programmable Gate Arrays, 2019Co-Authors: Ian Swarbrick, Dinesh D. Gaitonde, Sagheer Ahmad, Brian C. Gaide, Ygal ArbelAbstract:This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal-architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture Devices. These Devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) Devices. There is a trend in FPGA Devices of hardening many commonly used components such as processors, Memory controllers and other IO controllers. The next generation of Xilinx Devices take this a step further by providing a Device-Global Memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, FPGA fabric, Memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.
Ian Swarbrick - One of the best experts on this subject based on the ideXlab platform.
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FPGA - Network-on-Chip Programmable Platform in Versal TM ACAP Architecture
Proceedings of the 2019 ACM SIGDA International Symposium on Field-Programmable Gate Arrays, 2019Co-Authors: Ian Swarbrick, Dinesh D. Gaitonde, Sagheer Ahmad, Brian C. Gaide, Ygal ArbelAbstract:This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal-architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture Devices. These Devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) Devices. There is a trend in FPGA Devices of hardening many commonly used components such as processors, Memory controllers and other IO controllers. The next generation of Xilinx Devices take this a step further by providing a Device-Global Memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, FPGA fabric, Memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.
Javier Alejandro Varela - One of the best experts on this subject based on the ideXlab platform.
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IWOCL - Near Real-Time Risk Simulation of Complex Portfolios on Heterogeneous Computing Systems with OpenCL
Proceedings of the 5th International Workshop on OpenCL - IWOCL 2017, 2017Co-Authors: Javier Alejandro Varela, Norbert WehnAbstract:High-performance computing systems are highly required nowadays in financial risk analysis and management, which has become a key process at the core of financial institutions. Risk metrics such as portfolio value-at-risk and expected shortfall are computed on a daily basis. In this regard, the most general and flexible approach is a nested Monte Carlo simulation, which is very compute-intensive. In this work, we exploit the Open Computing Language (OpenCL) to efficiently map the nested simulation of complex portfolios with multiple algorithms on heterogeneous computing systems, maximizing system-level performance. The code portability and individual customizations allow us to profile the kernels on different accelerating platforms, such as CPU, Intel's Xeon Phi, and GPU. The combination of OpenCL, a new bit-accurate algorithmic optimization, and the extension of an existing numerical scheme using interpolation, allows us to achieve over 1000x speedup compared to the state-of-the-art approach, making this approach even feasible for intraday risk analysis. Our proposed system design also minimizes costly host-Device data transfers and the required Device Global Memory, enabling complex portfolios to be easily scaled.
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IPDPS Workshops - Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study
2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2017Co-Authors: Javier Alejandro Varela, Norbert Wehn, Qian Liang, Songyin TangAbstract:In the field of high performance heterogeneous computing systems, field programmable gate arrays (FPGAs) have shown great advantages in terms of acceleration and energy efficiency. And with the inclusion of the OpenCL framework for parallel programming, the design complexity has been greatly reduced. However, the parallel implementation of applications containing data-dependent branches usually experiences an important loss in performance, which affects all platforms alike. This data dependency leads the execution of parallel threads, also called work-items in OpenCL, to diverge. Whereas fixed architectures like CPU, GPU and Xeon Phi cannot efficiently cope with this divergent execution, the flexibility offered by FPGAs in terms of architecture can be exploited to tackle this problem. In this work, we present a new approach for FPGA implementations that decouples the parallel OpenCL work-items, avoiding the interference of data-dependent branches between them. We also demonstrate the necessary workarounds to obtain the maximum performance in a pipelined design, when unpredictable for-loop exit conditions are caused by the data dependency. Furthermore, we show how to efficiently interleave computation with transfers to Device Global Memory in each work-item. This approach is then evaluated with a real-life case study from Finance, with four different configurations implemented on FPGA with Xilinx SDAccel, and compared to the optimized implementation on CPU, GPU, and Xeon Phi. Our results show that FPGAs can deliver up to 5.5x speedup, whereas the system-level energy efficiency increases between 2x and 9.5x in all cases.
Norbert Wehn - One of the best experts on this subject based on the ideXlab platform.
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IWOCL - Near Real-Time Risk Simulation of Complex Portfolios on Heterogeneous Computing Systems with OpenCL
Proceedings of the 5th International Workshop on OpenCL - IWOCL 2017, 2017Co-Authors: Javier Alejandro Varela, Norbert WehnAbstract:High-performance computing systems are highly required nowadays in financial risk analysis and management, which has become a key process at the core of financial institutions. Risk metrics such as portfolio value-at-risk and expected shortfall are computed on a daily basis. In this regard, the most general and flexible approach is a nested Monte Carlo simulation, which is very compute-intensive. In this work, we exploit the Open Computing Language (OpenCL) to efficiently map the nested simulation of complex portfolios with multiple algorithms on heterogeneous computing systems, maximizing system-level performance. The code portability and individual customizations allow us to profile the kernels on different accelerating platforms, such as CPU, Intel's Xeon Phi, and GPU. The combination of OpenCL, a new bit-accurate algorithmic optimization, and the extension of an existing numerical scheme using interpolation, allows us to achieve over 1000x speedup compared to the state-of-the-art approach, making this approach even feasible for intraday risk analysis. Our proposed system design also minimizes costly host-Device data transfers and the required Device Global Memory, enabling complex portfolios to be easily scaled.
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IPDPS Workshops - Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study
2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2017Co-Authors: Javier Alejandro Varela, Norbert Wehn, Qian Liang, Songyin TangAbstract:In the field of high performance heterogeneous computing systems, field programmable gate arrays (FPGAs) have shown great advantages in terms of acceleration and energy efficiency. And with the inclusion of the OpenCL framework for parallel programming, the design complexity has been greatly reduced. However, the parallel implementation of applications containing data-dependent branches usually experiences an important loss in performance, which affects all platforms alike. This data dependency leads the execution of parallel threads, also called work-items in OpenCL, to diverge. Whereas fixed architectures like CPU, GPU and Xeon Phi cannot efficiently cope with this divergent execution, the flexibility offered by FPGAs in terms of architecture can be exploited to tackle this problem. In this work, we present a new approach for FPGA implementations that decouples the parallel OpenCL work-items, avoiding the interference of data-dependent branches between them. We also demonstrate the necessary workarounds to obtain the maximum performance in a pipelined design, when unpredictable for-loop exit conditions are caused by the data dependency. Furthermore, we show how to efficiently interleave computation with transfers to Device Global Memory in each work-item. This approach is then evaluated with a real-life case study from Finance, with four different configurations implemented on FPGA with Xilinx SDAccel, and compared to the optimized implementation on CPU, GPU, and Xeon Phi. Our results show that FPGAs can deliver up to 5.5x speedup, whereas the system-level energy efficiency increases between 2x and 9.5x in all cases.
Dinesh D. Gaitonde - One of the best experts on this subject based on the ideXlab platform.
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FPGA - Network-on-Chip Programmable Platform in Versal TM ACAP Architecture
Proceedings of the 2019 ACM SIGDA International Symposium on Field-Programmable Gate Arrays, 2019Co-Authors: Ian Swarbrick, Dinesh D. Gaitonde, Sagheer Ahmad, Brian C. Gaide, Ygal ArbelAbstract:This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal-architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture Devices. These Devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) Devices. There is a trend in FPGA Devices of hardening many commonly used components such as processors, Memory controllers and other IO controllers. The next generation of Xilinx Devices take this a step further by providing a Device-Global Memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, FPGA fabric, Memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.