The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Rafael Salomao Da Silva - One of the best experts on this subject based on the ideXlab platform.
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a virtual prototype semihosting approach for early simulation of cyber physical systems
International Symposium on Computers and Communications, 2018Co-Authors: Bruno Prado, Daniel Oliveira Dantas, Kalil Araujo Bispo, Thiago Fontes, Gabriel Santana, Rafael Salomao Da SilvaAbstract:An early design space exploration of Cyber-Physical Systems (CPS) is a challenging task due to multi-domain areas and tight interaction of computing systems (cyber) and environment actuation, communication and sensing (physical). The CPS designer must be able to rapidly evaluate various solutions and to verify if project constraints were met. In this paper, we propose a CPS development framework based on Virtual Prototype (VP) to provide a high level of abstraction models to accurately simulate CPS behavior, using target independent semihosting interfaces and assessing performance and timing constraints. The experiments show a high timing accuracy in CoreMark and Dhrystone compute-intensive benchmarks and a low overhead in I/O intensive tasks for semihosting access of host resources, such as files and memory. An ECG heart rate detection case study was implemented using heterogeneous interfaces to demonstrate how hardware, human and software components can be seamlessly integrated to exchange real world data.
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ISCC - A Virtual Prototype Semihosting Approach for Early Simulation of Cyber-Physical Systems
2018 IEEE Symposium on Computers and Communications (ISCC), 2018Co-Authors: Bruno Prado, Daniel Oliveira Dantas, Kalil Araujo Bispo, Thiago Fontes, Gabriel Santana, Rafael Salomao Da SilvaAbstract:An early design space exploration of Cyber-Physical Systems (CPS) is a challenging task due to multi-domain areas and tight interaction of computing systems (cyber) and environment actuation, communication and sensing (physical). The CPS designer must be able to rapidly evaluate various solutions and to verify if project constraints were met. In this paper, we propose a CPS development framework based on Virtual Prototype (VP) to provide a high level of abstraction models to accurately simulate CPS behavior, using target independent semihosting interfaces and assessing performance and timing constraints. The experiments show a high timing accuracy in CoreMark and Dhrystone compute-intensive benchmarks and a low overhead in I/O intensive tasks for semihosting access of host resources, such as files and memory. An ECG heart rate detection case study was implemented using heterogeneous interfaces to demonstrate how hardware, human and software components can be seamlessly integrated to exchange real world data.
Bruno Prado - One of the best experts on this subject based on the ideXlab platform.
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a virtual prototype semihosting approach for early simulation of cyber physical systems
International Symposium on Computers and Communications, 2018Co-Authors: Bruno Prado, Daniel Oliveira Dantas, Kalil Araujo Bispo, Thiago Fontes, Gabriel Santana, Rafael Salomao Da SilvaAbstract:An early design space exploration of Cyber-Physical Systems (CPS) is a challenging task due to multi-domain areas and tight interaction of computing systems (cyber) and environment actuation, communication and sensing (physical). The CPS designer must be able to rapidly evaluate various solutions and to verify if project constraints were met. In this paper, we propose a CPS development framework based on Virtual Prototype (VP) to provide a high level of abstraction models to accurately simulate CPS behavior, using target independent semihosting interfaces and assessing performance and timing constraints. The experiments show a high timing accuracy in CoreMark and Dhrystone compute-intensive benchmarks and a low overhead in I/O intensive tasks for semihosting access of host resources, such as files and memory. An ECG heart rate detection case study was implemented using heterogeneous interfaces to demonstrate how hardware, human and software components can be seamlessly integrated to exchange real world data.
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ISCC - A Virtual Prototype Semihosting Approach for Early Simulation of Cyber-Physical Systems
2018 IEEE Symposium on Computers and Communications (ISCC), 2018Co-Authors: Bruno Prado, Daniel Oliveira Dantas, Kalil Araujo Bispo, Thiago Fontes, Gabriel Santana, Rafael Salomao Da SilvaAbstract:An early design space exploration of Cyber-Physical Systems (CPS) is a challenging task due to multi-domain areas and tight interaction of computing systems (cyber) and environment actuation, communication and sensing (physical). The CPS designer must be able to rapidly evaluate various solutions and to verify if project constraints were met. In this paper, we propose a CPS development framework based on Virtual Prototype (VP) to provide a high level of abstraction models to accurately simulate CPS behavior, using target independent semihosting interfaces and assessing performance and timing constraints. The experiments show a high timing accuracy in CoreMark and Dhrystone compute-intensive benchmarks and a low overhead in I/O intensive tasks for semihosting access of host resources, such as files and memory. An ECG heart rate detection case study was implemented using heterogeneous interfaces to demonstrate how hardware, human and software components can be seamlessly integrated to exchange real world data.
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SBCCI - HdSC: a fast and preemptive modeling for on host HdS development
Proceedings of the 24th symposium on Integrated circuits and systems design - SBCCI '11, 2011Co-Authors: Bruno Prado, Edna Barros, Thiago Figueiredo, André AzizAbstract:Abstract In modern embedded systems, the Hardware-dependent Software (HdS) plays a critical role due to its increasing complexity and development cost. To support HdS development starting in an initial system design phase, fast and accurate preemptive processor models should be provided for simulating the software using register level interface on the host machine environment. This paper presents a strategy for target processor modeling that enables HdS development using native tools running in the host machine. Our approach supports the specification of platform components such as bus data and interruption interfaces and platform specification features, which provides a fast and accurate modeling mechanism. A technique for instruction count estimates is being proposed, which is very accurate and supports the development of driver code plus interruption service routines at a very early design phase. Results demonstrate that a virtual platform specified using the proposed approach can perform fast and accurate software simulation running on host machine, without the need of ISS processor models. The experiments performed validate the proposed approach by showing its efficiency with about three orders of magnitude simulation speed up, including the Dhrystone benchmark in order to assess performance evaluation estimation.
Young-june Choi - One of the best experts on this subject based on the ideXlab platform.
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Dhrystone million instructions per second–based task offloading from smartwatch to smartphone:
International Journal of Distributed Sensor Networks, 2017Co-Authors: Jong Won Lee, Young-june ChoiAbstract:Wearable devices such as smartwatches are critical to energy consumption due to their small battery size. To reduce possible energy consumption for high computational tasks, task offloading is a solution, but smartwatches are usually connected to smartphones that are also exposed to energy-saving issues. To resolve this problem, we propose a task offloading model that compares the energy efficiency of two cases: offloading or no offloading. When a task is offloaded, energy of a smartphone is sacrificed instead of a smartwatch, and additional energy is used for the communication. To derive the condition of an offloading, the size of a task could be considered, but it is impossible to estimate accurate energy due to various computational specifications of smartphones as well as smartwatches. To generalize the task size for different CPU conditions, we propose to use Dhrystone million instructions per second. The proposed model was evaluated through our testbed and confirmed that it shows a reasonable offloa...
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Dhrystone million instructions per second based task offloading from smartwatch to smartphone
International Journal of Distributed Sensor Networks, 2017Co-Authors: Jong Won Lee, Young-june ChoiAbstract:Wearable devices such as smartwatches are critical to energy consumption due to their small battery size. To reduce possible energy consumption for high computational tasks, task offloading is a solution, but smartwatches are usually connected to smartphones that are also exposed to energy-saving issues. To resolve this problem, we propose a task offloading model that compares the energy efficiency of two cases: offloading or no offloading. When a task is offloaded, energy of a smartphone is sacrificed instead of a smartwatch, and additional energy is used for the communication. To derive the condition of an offloading, the size of a task could be considered, but it is impossible to estimate accurate energy due to various computational specifications of smartphones as well as smartwatches. To generalize the task size for different CPU conditions, we propose to use Dhrystone million instructions per second. The proposed model was evaluated through our testbed and confirmed that it shows a reasonable offloa...
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UbiComp/ISWC Adjunct - Computation offloading for energy efficiency of smart devices
Proceedings of the 2017 ACM International Joint Conference on Pervasive and Ubiquitous Computing and Proceedings of the 2017 ACM International Symposi, 2017Co-Authors: Jong Won Lee, Young-june ChoiAbstract:Computation offloading provides efficiency of computation time and energy but at the cost of additional communication from wearable devices to servers, which may drain more energy of wearable devices. To derive the condition of computation offloading, we use a workload measurement model based on DMIPS (Dhrystone Millions of Instructions per Second) and compare the energy in offloading with the energy in not offloading. Using such a computation offloading decision model, in this paper, we propose a double computation offloading technique that offloads from wearable devices to smartphones and further offloads to cloud servers. For three experimental scenarios, we measured the energy consumption of each wearable or smart device and analyzed the energy efficiency of our model.
T. Nanya - One of the best experts on this subject based on the ideXlab platform.
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ICCD - TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model
Proceedings International Conference on Computer Design VLSI in Computers and Processors, 1Co-Authors: A. Takamura, M. Kuwako, Masashi Imai, T. Fujii, M. Ozawa, I. Fukasaku, Y. Ueno, T. NanyaAbstract:Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the design, chip implementation, and evaluation results of a 32-bit asynchronous microprocessor TITAC-2 whose instruction set is based on the MIPS R2000. The measured performance of TITAC-2 is 52.3 MIPS using the Dhrystone V2.1 benchmark.
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TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
1Co-Authors: A. Takamura, M. Kuwako, Masashi Imai, T. Fujii, M. Ozawa, I. Fukasaku, Y. Ueno, T. NanyaAbstract:Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the design, chip implementation, and evaluation results of a 32-bit asynchronous microprocessor TITAC-2 whose instruction set is based on the MIPS R2000. The measured performance of TITAC-2 is 52.3MIPS using the Dhrystone V2.1 benchmark. 1 Introduction Projecting forward from today, several reports suggest that, in 10 years, the CMOS technology will reach a point where the switching delay for a single gate is close to 10 picoseconds while a single chip area is nearly 10 square centimeters, with wiring moving into dominance[1]. The dominant wiring delay poses a fundamental limitation on synchronous syste..
Gabriel Santana - One of the best experts on this subject based on the ideXlab platform.
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a virtual prototype semihosting approach for early simulation of cyber physical systems
International Symposium on Computers and Communications, 2018Co-Authors: Bruno Prado, Daniel Oliveira Dantas, Kalil Araujo Bispo, Thiago Fontes, Gabriel Santana, Rafael Salomao Da SilvaAbstract:An early design space exploration of Cyber-Physical Systems (CPS) is a challenging task due to multi-domain areas and tight interaction of computing systems (cyber) and environment actuation, communication and sensing (physical). The CPS designer must be able to rapidly evaluate various solutions and to verify if project constraints were met. In this paper, we propose a CPS development framework based on Virtual Prototype (VP) to provide a high level of abstraction models to accurately simulate CPS behavior, using target independent semihosting interfaces and assessing performance and timing constraints. The experiments show a high timing accuracy in CoreMark and Dhrystone compute-intensive benchmarks and a low overhead in I/O intensive tasks for semihosting access of host resources, such as files and memory. An ECG heart rate detection case study was implemented using heterogeneous interfaces to demonstrate how hardware, human and software components can be seamlessly integrated to exchange real world data.
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ISCC - A Virtual Prototype Semihosting Approach for Early Simulation of Cyber-Physical Systems
2018 IEEE Symposium on Computers and Communications (ISCC), 2018Co-Authors: Bruno Prado, Daniel Oliveira Dantas, Kalil Araujo Bispo, Thiago Fontes, Gabriel Santana, Rafael Salomao Da SilvaAbstract:An early design space exploration of Cyber-Physical Systems (CPS) is a challenging task due to multi-domain areas and tight interaction of computing systems (cyber) and environment actuation, communication and sensing (physical). The CPS designer must be able to rapidly evaluate various solutions and to verify if project constraints were met. In this paper, we propose a CPS development framework based on Virtual Prototype (VP) to provide a high level of abstraction models to accurately simulate CPS behavior, using target independent semihosting interfaces and assessing performance and timing constraints. The experiments show a high timing accuracy in CoreMark and Dhrystone compute-intensive benchmarks and a low overhead in I/O intensive tasks for semihosting access of host resources, such as files and memory. An ECG heart rate detection case study was implemented using heterogeneous interfaces to demonstrate how hardware, human and software components can be seamlessly integrated to exchange real world data.