The Experts below are selected from a list of 282 Experts worldwide ranked by ideXlab platform
Tomokazu Morita - One of the best experts on this subject based on the ideXlab platform.
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error correction circuit using Difference Set cyclic code
Asia and South Pacific Design Automation Conference, 2003Co-Authors: Yukihiro Kato, Tomokazu MoritaAbstract:An error correction receiver using Difference-Set cyclic code has been designed. Highly reliable operation, short critical path, and small circuit size are key issues. The synchronization circuit is optimized in its circuit size by detecting 10 kinds of bit sequences for synchronization. The circuit action is governed by state machine combined with a Johnson counter and a timer. The critical path length is estimated to be 4.8, which is less than average value.
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error correction circuit using Difference Set cyclic code
Asia and South Pacific Design Automation Conference, 2003Co-Authors: Yukihiro Kato, Tomokazu MoritaAbstract:An error correction receiver using a Difference-Set cyclic code has been designed. Highly reliable operation, short critical path, and small circuit size are key issues. The synchronization circuit is optimized in its circuit size by detecting 10 kinds of bit sequences for synchronization. The circuit action is governed by a state machine combined with a Johnson counter and a timer. The critical path length is estimated to be 4.8, which is less than the average value.
Juan Antonio Maestro - One of the best experts on this subject based on the ideXlab platform.
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An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016Co-Authors: Pedro Reviriego, Liyi Xiao, Shanshan Liu, Juan Antonio MaestroAbstract:Memories that operate in harsh environments, like for example space, suffer a significant number of errors. The error correction codes (ECCs) are routinely used to ensure that those errors do not cause data corruption. However, ECCs introduce overheads both in terms of memory bits and decoding time that limit speed. In particular, this is an issue for applications that require strong error correction capabilities. A number of recent works have proposed advanced ECCs, such as orthogonal Latin squares or Difference Set codes that can be decoded with relatively low delay. The price paid for the low decoding time is that in most cases, the codes are not optimal in terms of memory overhead and require more parity check bits. On the other hand, codes like the (24,12) Golay code that minimize the number of parity check bits have a more complex decoding. A compromise solution has been recently explored for Bose–Chaudhuri–Hocquenghem codes. The idea is to implement a fast parallel decoder to correct the most common error patterns (single and double adjacent) and use a slower serial decoder for the rest of the patterns. In this brief, it is shown that the same scheme can be efficiently implemented for the (24,12) Golay code. In this case, the properties of the Golay code can be exploited to implement a parallel decoder that corrects single- and double-adjacent errors that is faster and simpler than a single-error correction decoder. The evaluation results using a 65-nm library show significant reductions in area, power, and delay compared with the traditional decoder that can correct single and double-adjacent errors. In addition, the proposed decoder is also able to correct some triple-adjacent errors, thus covering the most common error patterns.
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comparison of the susceptibility to soft errors of sram based fpga error correction codes implementations
IEEE Transactions on Nuclear Science, 2012Co-Authors: G Sorrenti, Juan Antonio Maestro, P Reviriego, F Casini, M Alderighi, Hortensia MechaAbstract:Nowadays the reliability issues of SRAM-based Field Programmable Gate Arrays (FPGAs) operating in harsh environments are well understood. One major effect is Single Event UpSets (SEUs), which are able to invert the stored logical value in flip-flops and memory cells. This issue is more serious when the affected memory cells are part of the configuration memory used for programming the circuit functionality. The consequences may be alterations of the circuit functionality causing errors which may only be corrected by reprogramming the device. For a better understanding of the robustness of programmed circuits, this paper compares two decoders for Error Correction Codes (ECCs). A Hamming Decoder and a One-Step Majority Logic Decoder (OS-MLD) for the Difference-Set Cyclic Codes (DSCC) are analyzed yielding surprisingly unexpected results for their SEU susceptibility, which are interesting for application designers.
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multiple cell upSet correction in memories using Difference Set codes
IEEE Transactions on Circuits and Systems, 2012Co-Authors: Pedro Reviriego, Mark F Flanagan, Shihfu Liu, Juan Antonio MaestroAbstract:Error Correction Codes (ECCs) are commonly used to protect memories from soft errors. As technology scales, Multiple Cell UpSets (MCUs) become more common and affect a larger number of cells. An option to protect memories against MCUs is to use advanced ECCs that can correct more than one error per word. In this area, the use of one step majority logic decodable codes has recently been proposed for memory applications. Difference Set (DS) codes are one example of these codes. In this paper, a scheme is presented to protect a memory from MCUs using Difference Set codes. The proposed scheme exploits the localization of the errors in an MCU, as well as the properties of DS codes, to provide enhanced error correction capabilities. The properties of the DS codes are also used to reduce the decoding time. The scheme has been implemented in HDL, and circuit area and speed estimates are provided.
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a 64 45 triple error correction code for memory applications
IEEE Transactions on Device and Materials Reliability, 2012Co-Authors: Pedro Reviriego, Mark F Flanagan, Juan Antonio MaestroAbstract:Memories are commonly protected with error correction codes to avoid data corruption when a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This is because they are simple to implement and provide low latency. More advanced codes have been considered, but their main drawback is the complexity of the decoders and the added latency. Recently, the use of one-step majority logic decodable codes has been proposed for memory protection. One-step majority logic decoding enables the use of low-complexity decoders, and low latency can also be achieved with moderate complexity. The main issue is that there are only a few codes that are one-step majority logic decodable. This restricts the choice of word lengths and error correction capabilities. In this paper, a method to derive new codes from a class of one-step majority logic decodable codes known as Difference-Set codes is proposed. The derived codes can also be efficiently implemented. As an example, a (64,45) triple error correction (TEC) code is derived and compared with existing SEC and TEC codes. The results presented enable a wider choice of word lengths and error correction capabilities that will be useful for memory designs.
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efficient majority logic fault detection with Difference Set codes for memory applications
IEEE Transactions on Very Large Scale Integration Systems, 2012Co-Authors: Pedro Reviriego, Juan Antonio MaestroAbstract:Nowadays, single event upSets (SEUs) altering digital circuits are becoming a bigger concern for memory applications. This paper presents an error-detection method for Difference-Set cyclic codes with majority logic decoding. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low.
Yukihiro Kato - One of the best experts on this subject based on the ideXlab platform.
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error correction circuit using Difference Set cyclic code
Asia and South Pacific Design Automation Conference, 2003Co-Authors: Yukihiro Kato, Tomokazu MoritaAbstract:An error correction receiver using Difference-Set cyclic code has been designed. Highly reliable operation, short critical path, and small circuit size are key issues. The synchronization circuit is optimized in its circuit size by detecting 10 kinds of bit sequences for synchronization. The circuit action is governed by state machine combined with a Johnson counter and a timer. The critical path length is estimated to be 4.8, which is less than average value.
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error correction circuit using Difference Set cyclic code
Asia and South Pacific Design Automation Conference, 2003Co-Authors: Yukihiro Kato, Tomokazu MoritaAbstract:An error correction receiver using a Difference-Set cyclic code has been designed. Highly reliable operation, short critical path, and small circuit size are key issues. The synchronization circuit is optimized in its circuit size by detecting 10 kinds of bit sequences for synchronization. The circuit action is governed by a state machine combined with a Johnson counter and a timer. The critical path length is estimated to be 4.8, which is less than the average value.
Keqin Feng - One of the best experts on this subject based on the ideXlab platform.
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a new class of near optimal partial fourier codebooks from an almost Difference Set
Designs Codes and Cryptography, 2014Co-Authors: Keqin Feng, Aixian ZhangAbstract:An (N, K) codebook is a Set of N unit-norm code vectors in a K-dimensional vector space. Also known as a frame, it has many applications in communications, signal processing, and quantum computing. In the applications, it is required that the maximum magnitude of inner products between a pair of distinct code vectors should meet the Welch bound equality, strictly or asymptotically. In this paper, a new class of (N, K) partial Fourier codebooks is constructed from an almost Difference Set, where N = K 2 − 1 and K = p k for a prime p and a positive integer k. It turns out that the almost Difference Set is equivalent to a modular Golomb ruler, and is obtained by a Set of elements decimated from an N-ary Sidelnikov sequence of length N with decimation factor K − 1. In the codebook, the magnitude of inner products between distinct code vectors is two-valued, and its maximum nearly achieves the Welch bound equality, which leads to a near-optimal codebook or nearly equiangular tight frame. Equivalent to a K × N partial Fourier matrix with near-optimal coherence, the new partial Fourier codebook can find its potential applications in deterministic compressed sensing.
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construction of cyclotomic codebooks nearly meeting the welch bound
Designs Codes and Cryptography, 2012Co-Authors: Aixian Zhang, Keqin FengAbstract:Ding and Feng (IEEE Trans Inform Theory 52(9):4229---4235, 2006, IEEE Trans Inform Theory 53(11):4245---4250, 2007) constructed series of (N, K) codebooks which meet or nearly meet the Welch bound $${\sqrt{\frac{N-K}{(N-1)K}}}$$ by using Difference Set (DS) or almost Difference Set (ADS) in certain finite abelian group respectively. In this paper, we generalize the cyclotomic constructions considered in (IEEE Trans Inform Theory 52(9):4229---4235, 2006, IEEE Trans Inform Theory 53(11):4245---4250, 2007) and (IEEE Trans Inform Theory 52(5), 2052---2061, 2006) to present more series of codebooks which nearly meet the Welch bound under looser conditions than ones required by DS and ADS.
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two classes of codebooks nearly meeting the welch bound
IEEE Transactions on Information Theory, 2012Co-Authors: Aixian Zhang, Keqin FengAbstract:In this paper, the value of Imax(C) for codebooks C = C(D) constructed by certain almost Difference Sets D in Fqx is determined and expressed in terms of Jacobi sums from which it shows that such codebooks nearly meet the Welch bound. This result is an answer of a question raised by C.Ding and T.Feng in [2]. We also present another series of codebooks which nearly meet the Welch bound, where the codebook is constructed by a subSet R = Fq1 ⊕ Fq2. When q1 = q2, De is an almost Difference Set of R.
Seshan Srirangarajan - One of the best experts on this subject based on the ideXlab platform.
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co prime arrays and Difference Set analysis
European Signal Processing Conference, 2017Co-Authors: Usham V Dias, Seshan SrirangarajanAbstract:Co-prime arrays have gained in popularity as an efficient way to estimate second order statistics at the Nyquist rate from sub-Nyquist samples without any sparsity constraint. We derive an expression for the degrees of freedom and the number of consecutive values in the Difference Set for the prototype co-prime array. This work shows that, under the wide sense stationarity (WSS) condition, larger consecutive Difference values can be achieved by using the union of all the Difference Sets. We provide a closed-form expression in order to determine the number of sample pairs that are available for estimating the statistics for each value of the Difference Set, also known as the weight function. The estimation accuracy and latency depends on the number of sample pairs used for estimating the second order statistic. We also obtain the closed-form expression for the bias of the correlogram spectral estimate. Simulation results show that the co-prime based periodogram and biased correlogram estimate are equivalent, and the reconstruction using our proposed formulation provides lower latency.