The Experts below are selected from a list of 33 Experts worldwide ranked by ideXlab platform
Enrico Rubiola - One of the best experts on this subject based on the ideXlab platform.
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The sampling theorem in Pi and lambda Digital frequency Dividers
2013 Joint European Frequency and Time Forum & International Frequency Control Symposium (EFTF IFC), 2013Co-Authors: Claudio E. Calosso, Enrico RubiolaAbstract:It is a common belief that a noise-free frequency Divider by D scales down the input phase by a factor of 1/D, thus the phase-noise power spectral density (PSD) by 1/D2. We prove that the behavior described does not apply to Digital Dividers. Instead, the Digital Divider scales the white phase-noise PSD down by 1/D. Phase downsampling and aliasing, inherent in Digital frequency division, is the reason. However the 1/D2 law holds asymptotically for flicker, where the aliases can be neglected. We propose a new de-aliased Divider, which scales the input phase-noise PSD by approximately 1/D2. The scheme is surprisingly simple and suitable to CPLD and FPGA implementation.
M. Siccardi - One of the best experts on this subject based on the ideXlab platform.
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Power supply noise conversion to phase noise in CMOS frequency Digital Divider
Proceedings of the 2002 IEEE International Frequency Control Symposium and PDA Exhibition (Cat. No.02CH37234), 2002Co-Authors: J.d. Crockett, M. SiccardiAbstract:A Digital frequency Divider is a state machine that synthesizes a frequency sub multiple of a reference signal. While the Digital frequency Divider is a Digital circuit handling square waves, its input and output signals are usually sine waves; a sine wave to square wave front-end circuit is required to generate an appropriate clock signal for the flip flops in the Divider. In the first approximation the gate threshold voltage changes with power supply voltage and this voltage noise yields symmetrical duty cycle modulation of the gate output square-wave signal; that is, if it makes rising edges anticipate then the failing edges are delayed. Although zero crossing jitter is present, the sine wave signal obtained by filtering out the harmonics of the square wave fundamental component is amplitude modulated only and no phase modulation occurs. The picture changes when the square wave signal goes to a selective front edge Digital processor as a Digital frequency Divider, where rising or failing edges are used only. The Divider output signal loses the duty cycle symmetry and the entire waveform is jittered because of the power supply voltage changes. This results in phase modulation and therefore a power supply to phase sensitivity.
Claudio E. Calosso - One of the best experts on this subject based on the ideXlab platform.
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The sampling theorem in Pi and lambda Digital frequency Dividers
2013 Joint European Frequency and Time Forum & International Frequency Control Symposium (EFTF IFC), 2013Co-Authors: Claudio E. Calosso, Enrico RubiolaAbstract:It is a common belief that a noise-free frequency Divider by D scales down the input phase by a factor of 1/D, thus the phase-noise power spectral density (PSD) by 1/D2. We prove that the behavior described does not apply to Digital Dividers. Instead, the Digital Divider scales the white phase-noise PSD down by 1/D. Phase downsampling and aliasing, inherent in Digital frequency division, is the reason. However the 1/D2 law holds asymptotically for flicker, where the aliases can be neglected. We propose a new de-aliased Divider, which scales the input phase-noise PSD by approximately 1/D2. The scheme is surprisingly simple and suitable to CPLD and FPGA implementation.
J.d. Crockett - One of the best experts on this subject based on the ideXlab platform.
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Power supply noise conversion to phase noise in CMOS frequency Digital Divider
Proceedings of the 2002 IEEE International Frequency Control Symposium and PDA Exhibition (Cat. No.02CH37234), 2002Co-Authors: J.d. Crockett, M. SiccardiAbstract:A Digital frequency Divider is a state machine that synthesizes a frequency sub multiple of a reference signal. While the Digital frequency Divider is a Digital circuit handling square waves, its input and output signals are usually sine waves; a sine wave to square wave front-end circuit is required to generate an appropriate clock signal for the flip flops in the Divider. In the first approximation the gate threshold voltage changes with power supply voltage and this voltage noise yields symmetrical duty cycle modulation of the gate output square-wave signal; that is, if it makes rising edges anticipate then the failing edges are delayed. Although zero crossing jitter is present, the sine wave signal obtained by filtering out the harmonics of the square wave fundamental component is amplitude modulated only and no phase modulation occurs. The picture changes when the square wave signal goes to a selective front edge Digital processor as a Digital frequency Divider, where rising or failing edges are used only. The Divider output signal loses the duty cycle symmetry and the entire waveform is jittered because of the power supply voltage changes. This results in phase modulation and therefore a power supply to phase sensitivity.
Herbert Zirath - One of the best experts on this subject based on the ideXlab platform.
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Regenerative GaAs MMIC Frequency Dividers for 28 and 14 GHz
2000 30th European Microwave Conference, 2000Co-Authors: Lars Landen, Christian Fager, Herbert ZirathAbstract:The design and characterization of two regenerative frequency Dividers based on a commercial foundry GaAs HEMT-process are described. The Dividers are intended to be used in a 56 GHz phase locked frequency generator. The main goal is to design Dividers that have high input sensitivity and low DC-power consumption. The Dividers are regenerative and consist of a resistive mixer followed by a frequency selective amplifier. The regenerative Divider, compared to a Digital Divider, consumes less DC-power and has a higher operational frequency. The output of the amplifier is fed back into the LO-port of the mixer through a lumped element coupler. The Dividers occupy 4.5 mm2 each. Both Dividers deliver 7 dBm output power with a rejection of the fundamental frequency of more than 15 dB and a DC-power consumption of 100 mW. The 14 GHz and 28 GHz Dividers have 3 dB bandwidths of 11% and 5.7% respectively.