The Experts below are selected from a list of 122145 Experts worldwide ranked by ideXlab platform

Georges Gielen - One of the best experts on this subject based on the ideXlab platform.

  • Digital Domain chopping technique for high resolution pll based sensor interfaces
    Sensors and Actuators A-physical, 2016
    Co-Authors: Jorge Marin, J. Van Rethy, Johan Vergauwen, Georges Gielen
    Abstract:

    Abstract Due to their high compatibility with scaled CMOS and emerging technologies, highly-Digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancelation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a Digital-Domain chopping technique suited for offset and 1/f-noise cancelation in applications where medium-to-high-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10 dB of SNR gain per decade of oversampling as expected from theory.

  • Digital-Domain chopping technique for high-resolution PLL-based sensor interfaces ☆
    Sensors and Actuators A: Physical, 2016
    Co-Authors: Jorge Marin, J. Van Rethy, Johan Vergauwen, Georges Gielen
    Abstract:

    Abstract Due to their high compatibility with scaled CMOS and emerging technologies, highly-Digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancelation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a Digital-Domain chopping technique suited for offset and 1/f-noise cancelation in applications where medium-to-high-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10 dB of SNR gain per decade of oversampling as expected from theory.

  • Digital-Domain Chopping Technique for PLL-Based Sensor Interfaces
    Procedia Engineering, 2015
    Co-Authors: Jorge Marin, J. Van Rethy, Hans Danneels, Johan Vergauwen, Georges Gielen
    Abstract:

    Abstract Highly-Digital, time-/frequency-based architectures have become an attractive alternative to amplitude-based techniques for sensor interfaces due to their high time resolution, low power and area scalability potential. However, even though thermal noise can be addressed by applying oversampling, offset and 1/f noise limit the resolution at low frequencies. Therefore, dynamic offset cancellation techniques like chopping and autozeroing, used in traditional circuits, must be adapted to such time-based implementations. This paper presents a Digital-Domain chopping technique suited for offset and 1/f-noise cancellation in PLL-based sensor interfaces. System-level simulations demonstrate a resolution increase from 11 to 15 bits for a 200 Hz signal bandwidth.

  • BMAS - Modeling and simulation of a sigma-delta Digital to analog converter using VHDL-AMS
    Proceedings 2000 IEEE ACM International Workshop on Behavioral Modeling and Simulation, 1
    Co-Authors: Martin Vogels, B. De Smedt, Georges Gielen
    Abstract:

    Sigma-Delta Digital to analog converters are less vulnerable to circuit imperfections than their A/D counterparts because they have their noise-shaping loop all in the Digital Domain. Still the analog part of the system (basically a low-pass filter) can degrade the overall performance, especially in the case of multi-bit converters. This paper presents a way of identifying and simulating the major noise and harmonics contributions of the system using VHDL-AMS. The resulting system-level model can be used to explore different architectures in the Digital Domain and to determine the specifications of the different building blocks.

Hong-june Park - One of the best experts on this subject based on the ideXlab platform.

  • a Digital Domain calibration of split capacitor dac for a differential sar adc without additional analog circuits
    IEEE Transactions on Circuits and Systems, 2013
    Co-Authors: Jiyong Um, Eunwoo Song, Hong-june Park
    Abstract:

    A Digital-Domain calibration method is proposed for a split-capacitor DAC (split-CDAC) used in a differential-type 11-bit SAR ADC. It calibrates the nonlinearities of SAR ADC due to the DAC capacitance mismatch as well as the two parasitic capacitances connected in parallel with each of the bridge capacitor and the LSB bank of split-CDAC. The proposed ADC does not require any additional analog circuits for calibration, because it utilizes one of the two split-CDACs to measure the error codes of the other split-CDAC. During the normal A/D conversion step, the 11.5-bit raw SAR code output of ADC is added to the pre-measured error codes to generate the 11-bit calibrated output code. The analog block of the ADC was fabricated in a 0.13- μm CMOS process, and the Digital block was implemented in a FPGA. The measured SNDR and SFDR are 61.6 dB (ENOB 9.93 bits) and 78 dB at the Nyquist rate with a 5 kHz sine wave input. INL and DNL are measured to be +0.96/-0.98 LSB, and +0.96/-0.97 LSB, respectively. This work extends the prior work by utilizing an additional 0.5-bit raw SAR code to eliminate the missing code, and by employing a temporal averaging with a FIR LPF to measure the error code reliably in spite of the supply noise.

  • A-SSCC - Digital-Domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC
    IEEE Asian Solid-State Circuits Conference 2011, 2011
    Co-Authors: Jae Hwan Kim, Jae-yoon Sim, Hong-june Park
    Abstract:

    A Digital-Domain calibration is proposed for a split-capacitor DAC of a 0.5 V 11 bit 10 kS/s differential-type SAR ADC. The calibration improves the linearity of ADC, especially INL by +1.59/-1.71 LSB, SFDR by 19.1 dB, and SNDR by 5.0 dB (ENOB by 0.83 bits). It compensates both the mismatch among binary-weighted capacitors and the errors due to parasitic capacitance of bridge-capacitor and LSB bank. No extra calibration DAC is required in this work, because one of the two differential DAC branches is used to measure errors of the other DAC branch. Measurements on the fabricated chip with a 0.13 mm CMOS process show INL +0.78/-0.89 LSB, DNL +0.75/-0.89 LSB, SNDR 61.7 dB (ENOB 9.96 bits), and SFDR 81.8 dB at the Nyquist rate. The power consumption and FoM of analog block are 560 nW and 55 fJ/conversion-step, respectively.

Jorge Marin - One of the best experts on this subject based on the ideXlab platform.

  • Digital Domain chopping technique for high resolution pll based sensor interfaces
    Sensors and Actuators A-physical, 2016
    Co-Authors: Jorge Marin, J. Van Rethy, Johan Vergauwen, Georges Gielen
    Abstract:

    Abstract Due to their high compatibility with scaled CMOS and emerging technologies, highly-Digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancelation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a Digital-Domain chopping technique suited for offset and 1/f-noise cancelation in applications where medium-to-high-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10 dB of SNR gain per decade of oversampling as expected from theory.

  • Digital-Domain chopping technique for high-resolution PLL-based sensor interfaces ☆
    Sensors and Actuators A: Physical, 2016
    Co-Authors: Jorge Marin, J. Van Rethy, Johan Vergauwen, Georges Gielen
    Abstract:

    Abstract Due to their high compatibility with scaled CMOS and emerging technologies, highly-Digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancelation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a Digital-Domain chopping technique suited for offset and 1/f-noise cancelation in applications where medium-to-high-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10 dB of SNR gain per decade of oversampling as expected from theory.

  • Digital-Domain Chopping Technique for PLL-Based Sensor Interfaces
    Procedia Engineering, 2015
    Co-Authors: Jorge Marin, J. Van Rethy, Hans Danneels, Johan Vergauwen, Georges Gielen
    Abstract:

    Abstract Highly-Digital, time-/frequency-based architectures have become an attractive alternative to amplitude-based techniques for sensor interfaces due to their high time resolution, low power and area scalability potential. However, even though thermal noise can be addressed by applying oversampling, offset and 1/f noise limit the resolution at low frequencies. Therefore, dynamic offset cancellation techniques like chopping and autozeroing, used in traditional circuits, must be adapted to such time-based implementations. This paper presents a Digital-Domain chopping technique suited for offset and 1/f-noise cancellation in PLL-based sensor interfaces. System-level simulations demonstrate a resolution increase from 11 to 15 bits for a 200 Hz signal bandwidth.

Jiyong Um - One of the best experts on this subject based on the ideXlab platform.

  • a Digital Domain calibration of split capacitor dac for a differential sar adc without additional analog circuits
    IEEE Transactions on Circuits and Systems, 2013
    Co-Authors: Jiyong Um, Eunwoo Song, Hong-june Park
    Abstract:

    A Digital-Domain calibration method is proposed for a split-capacitor DAC (split-CDAC) used in a differential-type 11-bit SAR ADC. It calibrates the nonlinearities of SAR ADC due to the DAC capacitance mismatch as well as the two parasitic capacitances connected in parallel with each of the bridge capacitor and the LSB bank of split-CDAC. The proposed ADC does not require any additional analog circuits for calibration, because it utilizes one of the two split-CDACs to measure the error codes of the other split-CDAC. During the normal A/D conversion step, the 11.5-bit raw SAR code output of ADC is added to the pre-measured error codes to generate the 11-bit calibrated output code. The analog block of the ADC was fabricated in a 0.13- μm CMOS process, and the Digital block was implemented in a FPGA. The measured SNDR and SFDR are 61.6 dB (ENOB 9.93 bits) and 78 dB at the Nyquist rate with a 5 kHz sine wave input. INL and DNL are measured to be +0.96/-0.98 LSB, and +0.96/-0.97 LSB, respectively. This work extends the prior work by utilizing an additional 0.5-bit raw SAR code to eliminate the missing code, and by employing a temporal averaging with a FIR LPF to measure the error code reliably in spite of the supply noise.

Johan Vergauwen - One of the best experts on this subject based on the ideXlab platform.

  • Digital Domain chopping technique for high resolution pll based sensor interfaces
    Sensors and Actuators A-physical, 2016
    Co-Authors: Jorge Marin, J. Van Rethy, Johan Vergauwen, Georges Gielen
    Abstract:

    Abstract Due to their high compatibility with scaled CMOS and emerging technologies, highly-Digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancelation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a Digital-Domain chopping technique suited for offset and 1/f-noise cancelation in applications where medium-to-high-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10 dB of SNR gain per decade of oversampling as expected from theory.

  • Digital-Domain chopping technique for high-resolution PLL-based sensor interfaces ☆
    Sensors and Actuators A: Physical, 2016
    Co-Authors: Jorge Marin, J. Van Rethy, Johan Vergauwen, Georges Gielen
    Abstract:

    Abstract Due to their high compatibility with scaled CMOS and emerging technologies, highly-Digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancelation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a Digital-Domain chopping technique suited for offset and 1/f-noise cancelation in applications where medium-to-high-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10 dB of SNR gain per decade of oversampling as expected from theory.

  • Digital-Domain Chopping Technique for PLL-Based Sensor Interfaces
    Procedia Engineering, 2015
    Co-Authors: Jorge Marin, J. Van Rethy, Hans Danneels, Johan Vergauwen, Georges Gielen
    Abstract:

    Abstract Highly-Digital, time-/frequency-based architectures have become an attractive alternative to amplitude-based techniques for sensor interfaces due to their high time resolution, low power and area scalability potential. However, even though thermal noise can be addressed by applying oversampling, offset and 1/f noise limit the resolution at low frequencies. Therefore, dynamic offset cancellation techniques like chopping and autozeroing, used in traditional circuits, must be adapted to such time-based implementations. This paper presents a Digital-Domain chopping technique suited for offset and 1/f-noise cancellation in PLL-based sensor interfaces. System-level simulations demonstrate a resolution increase from 11 to 15 bits for a 200 Hz signal bandwidth.