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Andreas Kaiser - One of the best experts on this subject based on the ideXlab platform.
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Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI
IEEE Transactions on Microwave Theory and Techniques, 2019Co-Authors: Razvan-cristian Marin, Antoine Frappé, Philippe Cathelin, Andreia Cathelin, Bruno Stefanelli, Andreas KaiserAbstract:This paper presents a single-bit RF Transmitter based on single-bit switched-capacitor RF Digital-to-analog converters (DACs) embedded in an finite-impulse response (FIR) filter (FIR-DACs). The Transmitter system comprises a single-bit quadrature delta-sigma modulator (M), a Digital mixer, and a 109-tap RF FIR-DAC stage with a single external inductor, combining D-A conversion with discrete-and continuous-time filtering. The on-chip part of the FIR-DAC is built exclusively with CMOS inverters and metal-oxide-metal capacitors, which are implemented in the interconnect layers to propose a compact fully Digital solution, suitable for advanced CMOS nodes. A method for canceling redundant switching in the FIR-DAC is proposed to reduce its complexity and power consumption. Combining discrete-and continuous-time filtering, the out-of-band quantization noise of the 1-bit RF signal is strongly attenuated below the level required by emission masks. The RF FIR-DAC prototype is implemented in a 28-nm FD-SOI CMOS technology with ten metal layers and occupies a total active area of only 0.047 mm 2. The overall power consumption is 38 mW at 4.6-dBm peak output power, 900-MHz carrier frequency, and 1-V supply. FD-SOI body bias V t tuning is used to effectively correct mixing clock duty-cycle errors in order to perform precise high-frequency I/Q interleaving, which enables high image and local oscillator rejections. The resulting power consumption, surface, and performance of the measured prototype make the proposed circuits and concepts particularly appropriate for use in emerging Internet of Things (IoT) applications. Index Terms-28-nm FD-SOI, all-Digital Transmitter, body bias, delta-sigma modulation (M), finite-impulse response filter (FIR), finite-impulse response Digital-to-analog converter (FIR-DAC), switched-capacitor (SC) DAC.
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All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018Co-Authors: Fikre Tsigabu Gebreyohannes, Antoine Frappé, Philippe Cathelin, Andreas Kaiser, Andreia CathelinAbstract:This paper presents a novel Transmitter architecture which is tailored for low power, all-Digital, and high speed implementation. It is based on two-path parallel Digital-to-analog converters (DAC) which are driven by 180 • phase-shifted clocks. The architecture operates in high pass mode and extends the output carrier frequency up to half the DAC clock rate. To decrease the number of analog unit current cells in the converter, a low-pass-modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear Digital-to-analog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the-modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below −22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-Digital Transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes.
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Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018Co-Authors: Razvan-cristian Marin, Antoine Frappé, Andreas KaiserAbstract:This paper presents a complex delta-sigma modu-lator (CDSM) designed for integration in a Digital Transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a DSM has the advantage of increased performance in terms of signal-to-noise-ratio in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the subsequent filtering stage. This constraint could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross coupling the in-phase (I) and quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross couplings from the I and Q quantizers outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20-30-dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient coarse/fine configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths. Index Terms-Delta sigma modulator (DSM), complex delta sigma modulator (CDSM), finite impulse response (FIR), multi-standard coexistence, Digital Transmitter.
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Considerations for High-Speed Configurable- bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI
2015Co-Authors: Razvan-cristian Marin, Antoine Frappé, Andreas Kaiser, Andreia CathelinAbstract:This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a Digital Transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulator's configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different numbers of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.
Andreia Cathelin - One of the best experts on this subject based on the ideXlab platform.
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Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI
IEEE Transactions on Microwave Theory and Techniques, 2019Co-Authors: Razvan-cristian Marin, Antoine Frappé, Philippe Cathelin, Andreia Cathelin, Bruno Stefanelli, Andreas KaiserAbstract:This paper presents a single-bit RF Transmitter based on single-bit switched-capacitor RF Digital-to-analog converters (DACs) embedded in an finite-impulse response (FIR) filter (FIR-DACs). The Transmitter system comprises a single-bit quadrature delta-sigma modulator (M), a Digital mixer, and a 109-tap RF FIR-DAC stage with a single external inductor, combining D-A conversion with discrete-and continuous-time filtering. The on-chip part of the FIR-DAC is built exclusively with CMOS inverters and metal-oxide-metal capacitors, which are implemented in the interconnect layers to propose a compact fully Digital solution, suitable for advanced CMOS nodes. A method for canceling redundant switching in the FIR-DAC is proposed to reduce its complexity and power consumption. Combining discrete-and continuous-time filtering, the out-of-band quantization noise of the 1-bit RF signal is strongly attenuated below the level required by emission masks. The RF FIR-DAC prototype is implemented in a 28-nm FD-SOI CMOS technology with ten metal layers and occupies a total active area of only 0.047 mm 2. The overall power consumption is 38 mW at 4.6-dBm peak output power, 900-MHz carrier frequency, and 1-V supply. FD-SOI body bias V t tuning is used to effectively correct mixing clock duty-cycle errors in order to perform precise high-frequency I/Q interleaving, which enables high image and local oscillator rejections. The resulting power consumption, surface, and performance of the measured prototype make the proposed circuits and concepts particularly appropriate for use in emerging Internet of Things (IoT) applications. Index Terms-28-nm FD-SOI, all-Digital Transmitter, body bias, delta-sigma modulation (M), finite-impulse response filter (FIR), finite-impulse response Digital-to-analog converter (FIR-DAC), switched-capacitor (SC) DAC.
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All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018Co-Authors: Fikre Tsigabu Gebreyohannes, Antoine Frappé, Philippe Cathelin, Andreas Kaiser, Andreia CathelinAbstract:This paper presents a novel Transmitter architecture which is tailored for low power, all-Digital, and high speed implementation. It is based on two-path parallel Digital-to-analog converters (DAC) which are driven by 180 • phase-shifted clocks. The architecture operates in high pass mode and extends the output carrier frequency up to half the DAC clock rate. To decrease the number of analog unit current cells in the converter, a low-pass-modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear Digital-to-analog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the-modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below −22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-Digital Transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes.
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Considerations for High-Speed Configurable- bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI
2015Co-Authors: Razvan-cristian Marin, Antoine Frappé, Andreas Kaiser, Andreia CathelinAbstract:This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a Digital Transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulator's configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different numbers of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.
Antoine Frappé - One of the best experts on this subject based on the ideXlab platform.
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Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI
IEEE Transactions on Microwave Theory and Techniques, 2019Co-Authors: Razvan-cristian Marin, Antoine Frappé, Philippe Cathelin, Andreia Cathelin, Bruno Stefanelli, Andreas KaiserAbstract:This paper presents a single-bit RF Transmitter based on single-bit switched-capacitor RF Digital-to-analog converters (DACs) embedded in an finite-impulse response (FIR) filter (FIR-DACs). The Transmitter system comprises a single-bit quadrature delta-sigma modulator (M), a Digital mixer, and a 109-tap RF FIR-DAC stage with a single external inductor, combining D-A conversion with discrete-and continuous-time filtering. The on-chip part of the FIR-DAC is built exclusively with CMOS inverters and metal-oxide-metal capacitors, which are implemented in the interconnect layers to propose a compact fully Digital solution, suitable for advanced CMOS nodes. A method for canceling redundant switching in the FIR-DAC is proposed to reduce its complexity and power consumption. Combining discrete-and continuous-time filtering, the out-of-band quantization noise of the 1-bit RF signal is strongly attenuated below the level required by emission masks. The RF FIR-DAC prototype is implemented in a 28-nm FD-SOI CMOS technology with ten metal layers and occupies a total active area of only 0.047 mm 2. The overall power consumption is 38 mW at 4.6-dBm peak output power, 900-MHz carrier frequency, and 1-V supply. FD-SOI body bias V t tuning is used to effectively correct mixing clock duty-cycle errors in order to perform precise high-frequency I/Q interleaving, which enables high image and local oscillator rejections. The resulting power consumption, surface, and performance of the measured prototype make the proposed circuits and concepts particularly appropriate for use in emerging Internet of Things (IoT) applications. Index Terms-28-nm FD-SOI, all-Digital Transmitter, body bias, delta-sigma modulation (M), finite-impulse response filter (FIR), finite-impulse response Digital-to-analog converter (FIR-DAC), switched-capacitor (SC) DAC.
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All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018Co-Authors: Fikre Tsigabu Gebreyohannes, Antoine Frappé, Philippe Cathelin, Andreas Kaiser, Andreia CathelinAbstract:This paper presents a novel Transmitter architecture which is tailored for low power, all-Digital, and high speed implementation. It is based on two-path parallel Digital-to-analog converters (DAC) which are driven by 180 • phase-shifted clocks. The architecture operates in high pass mode and extends the output carrier frequency up to half the DAC clock rate. To decrease the number of analog unit current cells in the converter, a low-pass-modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear Digital-to-analog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the-modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below −22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-Digital Transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes.
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Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018Co-Authors: Razvan-cristian Marin, Antoine Frappé, Andreas KaiserAbstract:This paper presents a complex delta-sigma modu-lator (CDSM) designed for integration in a Digital Transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a DSM has the advantage of increased performance in terms of signal-to-noise-ratio in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the subsequent filtering stage. This constraint could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross coupling the in-phase (I) and quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross couplings from the I and Q quantizers outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20-30-dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient coarse/fine configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths. Index Terms-Delta sigma modulator (DSM), complex delta sigma modulator (CDSM), finite impulse response (FIR), multi-standard coexistence, Digital Transmitter.
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Considerations for High-Speed Configurable- bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI
2015Co-Authors: Razvan-cristian Marin, Antoine Frappé, Andreas Kaiser, Andreia CathelinAbstract:This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a Digital Transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulator's configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different numbers of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.
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Génération numérique de signaux RF pour les terminaux de communication mobile par modulation delta-sigma
2007Co-Authors: Antoine FrappéAbstract:In the software defined radio context, a Digital Transmitter based on ΔΣ modulation is proposed. Its architecture is built around two oversampled 3rd-order lowpass Digital ΔΣ modulators that provide a multiplexed high-speed 1-bit data stream directly coding the RF signal in the Digital domain. The output stream can then be fed to an efficient switching-mode power amplifier. The UMTS standard has been taken as an application example and a Digital RF signal generator providing the 1-bit output stream at 7.8Gs/s has been designed in a 90nm CMOS technology. Redundant arithmetic with complementary signal paths, non-exact output quantization and anticipated output evaluation have been implemented to reach the high sampling rate. 3-phase differential dynamic logic clocked by a DLL has been used at the circuit level. The fabricated prototype Transmitter IC demonstrates full functionality up to a 4GHz main clock frequency, reaching a maximum bandwidth of 50MHz at 1GHz center frequency with a 3.1dBm peak output power. When using the first image band, the transmit band can be moved up to 3 GHz. With a 2.6GHz main clock frequency and 5MHz WCDMA modulated channel at a carrier frequency of 650MHz, a channel output power of -3.9dBm and 53.6dB of ACPR are obtained. With the same settings, a channel output power of -15.8dBm and an ACPR of 44.3dB is reached in the 1.95GHz image band, which fulfills minimum UMTS requirements. The chip active area is 0.15mm² and its power consumption is 69mW for a 2.6GHz operating clock frequency.
Razvan-cristian Marin - One of the best experts on this subject based on the ideXlab platform.
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Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI
IEEE Transactions on Microwave Theory and Techniques, 2019Co-Authors: Razvan-cristian Marin, Antoine Frappé, Philippe Cathelin, Andreia Cathelin, Bruno Stefanelli, Andreas KaiserAbstract:This paper presents a single-bit RF Transmitter based on single-bit switched-capacitor RF Digital-to-analog converters (DACs) embedded in an finite-impulse response (FIR) filter (FIR-DACs). The Transmitter system comprises a single-bit quadrature delta-sigma modulator (M), a Digital mixer, and a 109-tap RF FIR-DAC stage with a single external inductor, combining D-A conversion with discrete-and continuous-time filtering. The on-chip part of the FIR-DAC is built exclusively with CMOS inverters and metal-oxide-metal capacitors, which are implemented in the interconnect layers to propose a compact fully Digital solution, suitable for advanced CMOS nodes. A method for canceling redundant switching in the FIR-DAC is proposed to reduce its complexity and power consumption. Combining discrete-and continuous-time filtering, the out-of-band quantization noise of the 1-bit RF signal is strongly attenuated below the level required by emission masks. The RF FIR-DAC prototype is implemented in a 28-nm FD-SOI CMOS technology with ten metal layers and occupies a total active area of only 0.047 mm 2. The overall power consumption is 38 mW at 4.6-dBm peak output power, 900-MHz carrier frequency, and 1-V supply. FD-SOI body bias V t tuning is used to effectively correct mixing clock duty-cycle errors in order to perform precise high-frequency I/Q interleaving, which enables high image and local oscillator rejections. The resulting power consumption, surface, and performance of the measured prototype make the proposed circuits and concepts particularly appropriate for use in emerging Internet of Things (IoT) applications. Index Terms-28-nm FD-SOI, all-Digital Transmitter, body bias, delta-sigma modulation (M), finite-impulse response filter (FIR), finite-impulse response Digital-to-analog converter (FIR-DAC), switched-capacitor (SC) DAC.
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Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018Co-Authors: Razvan-cristian Marin, Antoine Frappé, Andreas KaiserAbstract:This paper presents a complex delta-sigma modu-lator (CDSM) designed for integration in a Digital Transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a DSM has the advantage of increased performance in terms of signal-to-noise-ratio in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the subsequent filtering stage. This constraint could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross coupling the in-phase (I) and quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross couplings from the I and Q quantizers outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20-30-dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient coarse/fine configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths. Index Terms-Delta sigma modulator (DSM), complex delta sigma modulator (CDSM), finite impulse response (FIR), multi-standard coexistence, Digital Transmitter.
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Considerations for High-Speed Configurable- bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI
2015Co-Authors: Razvan-cristian Marin, Antoine Frappé, Andreas Kaiser, Andreia CathelinAbstract:This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a Digital Transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulator's configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different numbers of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.
Makoto Takamiya - One of the best experts on this subject based on the ideXlab platform.
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Digital coil Transmitter coil with programmable radius for wireless powering robust against distance variation
IEEE Wireless Power Transfer Conference, 2018Co-Authors: Hao Qiu, Takayasu Sakurai, Yoshiaki Narusue, Yoshihiro Kawahara, Makoto TakamiyaAbstract:A wireless powering system robust against distance variation is required. In this paper, a Digital Transmitter (TX) coil, whose radius depends on the distance (d) between the TX and receiver (RX) coils, is proposed that maximizes the efficiency of wireless powering. Firstly, we analytically derived the optimum TX coil radius ($r\mathrm{T}\mathrm{X}$, 0PT) to maximize the coil-to-coil efficiency ($\eta$) by co-optimizing the coupling coefficient and the quality factors of the coils. It was found that $r\mathrm{T}\mathrm{X}$,0PT was approximately equal to d. Then, a practical implementation of the Digital TX coil, whose radius was electrically varied without mechanical motion, was proposed. It was found by a measurement that, compared with a conventional TX coil with a constant radius, the proposed Digital TX coil increased $\eta$ from 12% to 20% when d was four times the RX coil radius.
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Digital Transmitter Coil for Wireless Power Transfer Robust Against Variation of Distance and Lateral Misalignment
IEEE Transactions on Microwave Theory and Techniques, 1Co-Authors: Takayasu Sakurai, Makoto TakamiyaAbstract:A Digital Transmitter (TX) coil consisting of several subcoils connected in parallel is proposed in wireless power transfer (WPT) systems robust against the variation of distance and lateral misalignment. According to the position of the receiver coil, the radius of the Digital TX coil can be programed to its optimal value to achieve the maximum coil-to-coil efficiency. Moreover, targeting the wireless charging of mobile devices, we propose a practical design methodology for the Digital TX coil. It is concluded that the Digital TX coil consisting of two subcoils is an effective design and that the performance is not significantly improved by adding more subcoils. The optimal radius ratio of these two subcoils is 0.54. Furthermore, we implement the designed Digital TX coil in a prototype WPT system, including a power amplifier and a rectifier. Experimental results show that within a space with a maximum distance and lateral misalignment of 100 mm, the system efficiency is improved by the Digital TX coil and reaches a maximum value of 48%. Compared with using a conventional TX coil with a constant radius, the system efficiency shows an absolute improvement of up to 7%.