The Experts below are selected from a list of 252 Experts worldwide ranked by ideXlab platform
Santanu Kapat - One of the best experts on this subject based on the ideXlab platform.
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Constant off-Time Digital Current-Mode Controlled Boost Converters With Enhanced Stability Boundary
IEEE Transactions on Power Electronics, 2019Co-Authors: K. Hariharan, Santanu Kapat, Siddhartha MukhopadhyayAbstract:The right-half-plane (RHP) zero in a continuous conduction mode boost converter results in a significantly restricted closed-loop bandwidth (BW) for higher voltage gain and/or load current conditions. A compensating ramp is used for current-mode control (CMC), and a higher ramp slope degrades the BW. Variable-frequency digital CMC offers inherent current-loop stability and real-time tuning scope for higher closed-loop BW. However, the challenges are to select the sampling frequency and sampling instant of the output voltage with discontinuous ripple due to the Effective Series Resistance of the output capacitor, and its impact on stability. This paper shows that an event-based current-mode constant off-time digital modulator achieves superior stability and performance in a boost converter along with the reduced RHP zero effect over other digital CMC techniques. Using a discrete-time framework, the fast-scale stability conditions and small-signal models are analytically derived for various digital CMC techniques, which are validated using SIMPLIS simulation. A boost converter prototype is tested, and the analytical predictions are verified experimentally. Further, the analysis is extended to a non-inverting buck-boost converter.
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Analysing the effects due to discontinuous output-voltage ripple in a digitally current-mode controlled boost converter
IET Power Electronics, 2018Co-Authors: Amit Kumar Singha, Santanu KapatAbstract:Digital implementation of current-mode control (CMC) considers the outer voltage-loop in the digital domain, whereas the inner current-loop is kept either in the analogue domain in mixed-signal CMC (MCMC) or in the digital domain in fully digital CMC (DCMC). Under finite voltage-loop sampling, this study reports that the selection of sampling point can completely change the stability status of a boost converter with non-minimum phase behaviour, particularly in the presence of the Effective-Series-Resistance of the output capacitor. A discrete-time framework is proposed for fast-scale stability analysis in a boost converter, operating under continuous conduction mode. Further, discrete-time small-signal models are derived and design guidelines are proposed for both MCMC and DCMC architectures with enhanced stability for fast transient performance. Keeping in mind software-controlled DCMC, a considerably large sampling delay is considered, and its effect on the performance and stability is discussed. A boost converter prototype is tested and various DCMC schemes along the proposed design techniques are implemented using a field-programmable-gate-array device.
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A Unified Framework for Analysis and Design of a Digitally Current-Mode Controlled Buck Converter
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016Co-Authors: Amit Kumar Singha, Santanu KapatAbstract:Mixed-signal current-mode control (MCMC) implementation has been gaining popularity, because of the tuning flexibility using the digital voltage controller Gc(z) along with the fast-changing analog current controller. Generally a continuous-time frequency-domain approach is adopted for the design of Gc(z); however, this method often fails to capture sub-harmonic, more generally the fast-scale instability due to finite discretization effects. This paper derives approximate discrete-time models and proposes a unified framework to derive closed-form stability conditions and discrete-time small-signal models of a synchronous buck converter under MCMC. Considering the effects due to finite output-voltage sampling and the Effective Series Resistance (ESR) of the output capacitor, the stability boundary in MCMC is found to be significantly restricted compared to its analog counterpart. Further, design methods are proposed to enhance stability boundary with improved transient performance by tuning the controller directly in the digital domain. A buck converter prototype is made, and the MCMC technique is realized using an FPGA device. Analytical predictions are verified experimentally.
Massimo Barbaro - One of the best experts on this subject based on the ideXlab platform.
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A $\Delta \Sigma$ Dithering-Amplification-Based Identification Technique for Online SMPS
IEEE Transactions on Power Electronics, 2016Co-Authors: Andrea Congiu, Emanuele Bodano, Massimo BarbaroAbstract:A novel nonparametric system identification (SI) algorithm is described, focusing on PID-based control loops for buck converters with Effective Series Resistance (ESR) in the output filter. Dithering amplification effects on the control path are exploited during the steady-state converter operation. The noise injected is used to stimulate the loop reaction and to identify the output filter configuration. Oversampling-dithering features of third-order $\Delta \Sigma$ modulators are used to increase the DPWM resolution during the converter nominal operation and, moreover, as the core key to compute the SI algorithm. A modified structure of a noise shaper is used to handle the resolution of the SI algorithm over a range of the desired frequencies during the nonparametric identification. The SI algorithm comprises two steps: the first processing step extracts the resonant frequency, and the second extracts the ESR zero from the power spectrum density computation of the control feedback error. The SI method has been validated with different buck converter configurations, and has successfully been integrated and measured into a digitally controlled buck converters prototype for automotive safety application.
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A $\Delta \Sigma$ Dithering-Amplification-Based Identification Technique for Online SMPS
IEEE Transactions on Power Electronics, 2016Co-Authors: Andrea Congiu, Emanuele Bodano, Massimo BarbaroAbstract:A novel nonparametric system identification (SI) algorithm is described, focusing on PID-based control loops for buck converters with Effective Series Resistance (ESR) in the output filter. Dithering amplification effects on the control path are exploited during the steady-state converter operation. The noise injected is used to stimulate the loop reaction and to identify the output filter configuration. Oversampling-dithering features of third-order ΔΣ modulators are used to increase the DPWM resolution during the converter nominal operation and, moreover, as the core key to compute the SI algorithm. A modified structure of a noise shaper is used to handle the resolution of the SI algorithm over a range of the desired frequencies during the nonparametric identification. The SI algorithm comprises two steps: the first processing step extracts the resonant frequency, and the second extracts the ESR zero from the power spectrum density computation of the control feedback error. The SI method has been validated with different buck converter configurations, and has successfully been integrated and measured into a digitally controlled buck converters prototype for automotive safety application.
Andrea Congiu - One of the best experts on this subject based on the ideXlab platform.
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A $\Delta \Sigma$ Dithering-Amplification-Based Identification Technique for Online SMPS
IEEE Transactions on Power Electronics, 2016Co-Authors: Andrea Congiu, Emanuele Bodano, Massimo BarbaroAbstract:A novel nonparametric system identification (SI) algorithm is described, focusing on PID-based control loops for buck converters with Effective Series Resistance (ESR) in the output filter. Dithering amplification effects on the control path are exploited during the steady-state converter operation. The noise injected is used to stimulate the loop reaction and to identify the output filter configuration. Oversampling-dithering features of third-order $\Delta \Sigma$ modulators are used to increase the DPWM resolution during the converter nominal operation and, moreover, as the core key to compute the SI algorithm. A modified structure of a noise shaper is used to handle the resolution of the SI algorithm over a range of the desired frequencies during the nonparametric identification. The SI algorithm comprises two steps: the first processing step extracts the resonant frequency, and the second extracts the ESR zero from the power spectrum density computation of the control feedback error. The SI method has been validated with different buck converter configurations, and has successfully been integrated and measured into a digitally controlled buck converters prototype for automotive safety application.
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A $\Delta \Sigma$ Dithering-Amplification-Based Identification Technique for Online SMPS
IEEE Transactions on Power Electronics, 2016Co-Authors: Andrea Congiu, Emanuele Bodano, Massimo BarbaroAbstract:A novel nonparametric system identification (SI) algorithm is described, focusing on PID-based control loops for buck converters with Effective Series Resistance (ESR) in the output filter. Dithering amplification effects on the control path are exploited during the steady-state converter operation. The noise injected is used to stimulate the loop reaction and to identify the output filter configuration. Oversampling-dithering features of third-order ΔΣ modulators are used to increase the DPWM resolution during the converter nominal operation and, moreover, as the core key to compute the SI algorithm. A modified structure of a noise shaper is used to handle the resolution of the SI algorithm over a range of the desired frequencies during the nonparametric identification. The SI algorithm comprises two steps: the first processing step extracts the resonant frequency, and the second extracts the ESR zero from the power spectrum density computation of the control feedback error. The SI method has been validated with different buck converter configurations, and has successfully been integrated and measured into a digitally controlled buck converters prototype for automotive safety application.
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Novel load identification techniques and a steady state self-tuning prototype for switching mode power supplies
2014Co-Authors: Andrea CongiuAbstract:Control of Switched Mode Power Supplies (SMPS) has been traditionally achieved through analog means with dedicated integrated circuits (ICs). However, as power systems are becoming increasingly complex, the classical concept of control has gradually evolved into the more general problem of power management, demanding functionalities that are hardly achievable in analog controllers. The high flexibility offered by digital controllers and their capability to implement sophisticated control strategies, together with the programmability of controller parameters, make digital control very attractive as an option for improving the features of dcdc converters. On the other side, digital controllers find their major weak point in the achievable dynamic performances of the closed loop system. Indeed, analogto-digital conversion times, computational delays and sampling-related delays strongly limit the small signal closed loop bandwidth of a digitally controlled SMPS. Quantization effects set other severe constraints not known to analog solutions. For these reasons, intensive scientific research activity is addressing the problem of making digital compensator stronger competitors against their analog counterparts in terms of achievable performances. In a wide range of applications, dcdc converters with high efficiency over the whole range of their load values are required. Integrated digital controllers for Switching Mode Power Supplies are gaining growing interest, since it has been shown the feasibility of digital controller ICs specifically developed for high frequency switching converters. One very interesting potential benefit is the use of autotuning of controller parameters (on-line controllers), so that the dynamic response can be set at the software level, independently of output capacitor filters, component variations and ageing. These kind of algorithms are able to identify the output filter configuration (system identification) and then automatically compute the best compensator gains to adjust system margins and bandwidth. In order to be an interesting solution, however, the self-tuning should satisfy two important requirements: it should not heavily affect converter operation under nominal condition and it should be based on a simple and robust algorithm whose complexity does not require a significant increase of the silicon area of the IC controller. The first issue is avoided performing the system identification (SI) with the system open loop configuration, where perturbations can be induced in the system before the start up. Much more challenging is to satisfy this requirement during steady state operations, where perturbations on the output voltage are limited by the regular operations of the converter. The main advantage of steady state SI methods, is the detection of possible non-idealities occurring during the converter operations. In this way, the system dynamics can be consequently adjusted with the compensator parameters tuning. The resource saving issue, requires the development of ad-hocself-tuning techniques specifically tailored for integrated digitally controlled converters. Considering the flexibility of digital control, self-tuning algorithms can be studied and easily integrated at hardware level into closed loop SMPS reducing development time and R & D costs. The work of this dissertation finds its origin in this context. Smart power management is accomplished by tuning the controller parameters accordingly to the identified converter configuration. Themain difficult for self-tuning techniques is the identification of the converter output filter configuration. Two novel system identification techniques have been validated in this dissertation. The open loop SI method is based on the system step response, while dithering amplification effects are exploited for the steady state SI method. The open loop method can be used as autotunig approach during or before the system start up, a step evolving reference voltage has been used as system perturbation and to obtain the output filter information with the Power Spectral Density (PSD) computation of the system step response. The use of ¢§ modulator is largely increasing in digital control feedback. During the steady state, the finite resolution introduces quantization effects on the signal path causing low frequency contributes of the digital control word. Through oversampling-dithering capabilities of ¢§ modulators, resolution improvements are obtained. The presented steady state identification techniques demonstrates that, amplifying the dithering effects on the signal path, the output filter information can be obtained on the digital side by processing with the PSD computation the perturbed output voltage. The amount of noise added on the output voltage does not affect the converter operations, mathematical considerations have been addressed and then justified both with a Matlab/Simulink fixed-point and a FPGA-based closed loop system. The load output filter identification of both algorithms, refer to the frequency domain. When the respective perturbations occurs, the system response is observed on the digital side and processed with the PSD computation. The extracted parameters are the resonant frequency ans the possible ESR (Effective Series Resistance) contributes,which can be detected as maximumin the PSD output. The SI methods have been validated for different configurations of buck converters on a fixed-point closed loop model, however, they can be easily applied to further converter configurations. The steady state method has been successfully integrated into a FPGA-based prototype for digitally controlled buck converters, that integrates a PSD computer needed for the load parameters identification. At this purpose, a novel VHDL-coded full-scalable hybrid processor for Constant Geometry FFT (CG-FFT) computation has been designed and integrated into the PSD computation system. The processor is based on a variation of the conventional algorithm used for FFT, which is the Constant-Geometry FFT (CG-FFT).Hybrid CORDIC-LUT scalable architectures, has been introduced as alternative approach for the twiddle factors (phase factors) computation needed during the FFT algorithms execution. The shared core architecture uses a single phase rotator to satisfy all TF requests. It can achieve improved logic saving by trading off with computational speed. The pipelined architecture is composed of a number of stages equal to the number of PEs and achieves the highest possible throughput, at the expense of more hardware usage.
Siddhartha Mukhopadhyay - One of the best experts on this subject based on the ideXlab platform.
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Constant off-Time Digital Current-Mode Controlled Boost Converters With Enhanced Stability Boundary
IEEE Transactions on Power Electronics, 2019Co-Authors: K. Hariharan, Santanu Kapat, Siddhartha MukhopadhyayAbstract:The right-half-plane (RHP) zero in a continuous conduction mode boost converter results in a significantly restricted closed-loop bandwidth (BW) for higher voltage gain and/or load current conditions. A compensating ramp is used for current-mode control (CMC), and a higher ramp slope degrades the BW. Variable-frequency digital CMC offers inherent current-loop stability and real-time tuning scope for higher closed-loop BW. However, the challenges are to select the sampling frequency and sampling instant of the output voltage with discontinuous ripple due to the Effective Series Resistance of the output capacitor, and its impact on stability. This paper shows that an event-based current-mode constant off-time digital modulator achieves superior stability and performance in a boost converter along with the reduced RHP zero effect over other digital CMC techniques. Using a discrete-time framework, the fast-scale stability conditions and small-signal models are analytically derived for various digital CMC techniques, which are validated using SIMPLIS simulation. A boost converter prototype is tested, and the analytical predictions are verified experimentally. Further, the analysis is extended to a non-inverting buck-boost converter.
Amit Kumar Singha - One of the best experts on this subject based on the ideXlab platform.
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Analysing the effects due to discontinuous output-voltage ripple in a digitally current-mode controlled boost converter
IET Power Electronics, 2018Co-Authors: Amit Kumar Singha, Santanu KapatAbstract:Digital implementation of current-mode control (CMC) considers the outer voltage-loop in the digital domain, whereas the inner current-loop is kept either in the analogue domain in mixed-signal CMC (MCMC) or in the digital domain in fully digital CMC (DCMC). Under finite voltage-loop sampling, this study reports that the selection of sampling point can completely change the stability status of a boost converter with non-minimum phase behaviour, particularly in the presence of the Effective-Series-Resistance of the output capacitor. A discrete-time framework is proposed for fast-scale stability analysis in a boost converter, operating under continuous conduction mode. Further, discrete-time small-signal models are derived and design guidelines are proposed for both MCMC and DCMC architectures with enhanced stability for fast transient performance. Keeping in mind software-controlled DCMC, a considerably large sampling delay is considered, and its effect on the performance and stability is discussed. A boost converter prototype is tested and various DCMC schemes along the proposed design techniques are implemented using a field-programmable-gate-array device.
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A Unified Framework for Analysis and Design of a Digitally Current-Mode Controlled Buck Converter
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016Co-Authors: Amit Kumar Singha, Santanu KapatAbstract:Mixed-signal current-mode control (MCMC) implementation has been gaining popularity, because of the tuning flexibility using the digital voltage controller Gc(z) along with the fast-changing analog current controller. Generally a continuous-time frequency-domain approach is adopted for the design of Gc(z); however, this method often fails to capture sub-harmonic, more generally the fast-scale instability due to finite discretization effects. This paper derives approximate discrete-time models and proposes a unified framework to derive closed-form stability conditions and discrete-time small-signal models of a synchronous buck converter under MCMC. Considering the effects due to finite output-voltage sampling and the Effective Series Resistance (ESR) of the output capacitor, the stability boundary in MCMC is found to be significantly restricted compared to its analog counterpart. Further, design methods are proposed to enhance stability boundary with improved transient performance by tuning the controller directly in the digital domain. A buck converter prototype is made, and the MCMC technique is realized using an FPGA device. Analytical predictions are verified experimentally.
