The Experts below are selected from a list of 4950 Experts worldwide ranked by ideXlab platform

David Droste - One of the best experts on this subject based on the ideXlab platform.

  • "ATE open system platform" IEEE-P1552 structured architecture for test systems (SATS)
    Proceedings AUTOTESTCON 2003. IEEE Systems Readiness Technology Conference., 2003
    Co-Authors: M.j. Stora, David Droste
    Abstract:

    The IEEE-P1552 structured architecture for test systems (SATS) standards effort, is a multidimensional ATE "open system platform" packaging specification. The standard defines data/signal/power interconnect mechanical/Electrical mating connector requirements and common hardware packaging form factors. Addressed are plug&play wiring panels, switchable instrument/power mezzanine (IPM) modules, high speed serial bus control, and test bus matrix functionality, that permit subelement interchangeability and interoperability. The standard's functional performance requirements are limited to mechanical engagement, connector styles/footprints, Electrical Pin characteristics, and Pin mapPing definitions. As a higher order plug&play architecture, SATS supports legacy VXIbus and PXIbus architectures as hybrid subsystem integrations.

  • IEEE-P1552 packaging architecture for computer-busboard systems (PACS)
    2001 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology Conference. (Cat. No.01CH37237), 1
    Co-Authors: M.j. Stora, David Droste
    Abstract:

    Initiated under IEEE-P1552 packaging architecture for computer-busboard systems (PACS) standards effort, this new electronic packaging specification extends the current two dimensional plug and play computer-based architecture of VMEbus, VXIbus, PCIbus, PXIbus, and several new standards into a three and four dimensional integrated hardware architecture. This extends power, control and signal forward front-to-back or back-to-front, in alignment with normal computer system serial functionality. Hardware interfaces relate primarily to packaging and data/signal/power interconnect mechanical/Electrical mating specifications, that should permit subelements to be interchanged without impact on subelement interoperability. The standard functional performance is limited to mechanical engagement, connector styles/footprints, Electrical Pin characteristics, and Pin mapPing definitions.

Haijun Huang - One of the best experts on this subject based on the ideXlab platform.

  • Hugoniot equation of state of cementite (Fe3C) up to 250 GPa and its geophysical implications
    Physics of the Earth and Planetary Interiors, 2020
    Co-Authors: Liu Xun, Lili Fan, Gang Yang, Xing Chen, Haijun Huang
    Abstract:

    Abstract Dense bulk Fe3C samples were synthesized by the high pressure–temperature method using a large-volume cubic press. The Hugoniot data of the Fe3C samples were measured from 65 to 250 GPa on a two-stage light gas gun. The shock velocities were measured by the Electrical Pin technique, and the particle velocities were calculated by the impedance match method. The shock velocity (Us) and particle velocity (Up) relationship of Fe3C was determined to be linear and described by Us = 4.77(7) + 1.60(2) Up. The thermal contributions of electronics and lattices were determined by first-principle simulation and thermodynamic calculation, respectively. Subsequently, the thermal equation of state of Fe3C was used to constrain the carbon amount in the inner core. We conclude that 2.9 ± 0.4 wt% carbon is needed to compensate for the density deficit between pure iron and the inner core, if carbon is the sole light element present in the core.

Dave Erskine - One of the best experts on this subject based on the ideXlab platform.

  • high pressure hugoniot of sapphire
    High‐pressure science and technology, 1994
    Co-Authors: Dave Erskine
    Abstract:

    The Hugoniot of sapphire was measured for the first time above 145 GPa, from 80 GPa to 340 GPa in shock‐wave experiments using projectiles accelerated by a two stage gas gun. The transit times of the shock waves were measured either optically with a streak camera or through Electrical Pin contacts. The Hugoniot in this pressure range fits Us=8.74+0.96 Up in km/s.

M.j. Stora - One of the best experts on this subject based on the ideXlab platform.

  • "ATE open system platform" IEEE-P1552 structured architecture for test systems (SATS)
    Proceedings AUTOTESTCON 2003. IEEE Systems Readiness Technology Conference., 2003
    Co-Authors: M.j. Stora, David Droste
    Abstract:

    The IEEE-P1552 structured architecture for test systems (SATS) standards effort, is a multidimensional ATE "open system platform" packaging specification. The standard defines data/signal/power interconnect mechanical/Electrical mating connector requirements and common hardware packaging form factors. Addressed are plug&play wiring panels, switchable instrument/power mezzanine (IPM) modules, high speed serial bus control, and test bus matrix functionality, that permit subelement interchangeability and interoperability. The standard's functional performance requirements are limited to mechanical engagement, connector styles/footprints, Electrical Pin characteristics, and Pin mapPing definitions. As a higher order plug&play architecture, SATS supports legacy VXIbus and PXIbus architectures as hybrid subsystem integrations.

  • IEEE-P1552 packaging architecture for computer-busboard systems (PACS)
    2001 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology Conference. (Cat. No.01CH37237), 1
    Co-Authors: M.j. Stora, David Droste
    Abstract:

    Initiated under IEEE-P1552 packaging architecture for computer-busboard systems (PACS) standards effort, this new electronic packaging specification extends the current two dimensional plug and play computer-based architecture of VMEbus, VXIbus, PCIbus, PXIbus, and several new standards into a three and four dimensional integrated hardware architecture. This extends power, control and signal forward front-to-back or back-to-front, in alignment with normal computer system serial functionality. Hardware interfaces relate primarily to packaging and data/signal/power interconnect mechanical/Electrical mating specifications, that should permit subelements to be interchanged without impact on subelement interoperability. The standard functional performance is limited to mechanical engagement, connector styles/footprints, Electrical Pin characteristics, and Pin mapPing definitions.

Wang Sheng-qiang - One of the best experts on this subject based on the ideXlab platform.

  • The Effect of Density in Composition B on Deflagration-Detonation-Transition Behavior
    Chinese Journal of Explosives and Propellants, 2006
    Co-Authors: Wen Shang-gang, Wang Sheng-qiang
    Abstract:

    The composition B applied widely in conventional weapons was chosen as the object of this research.By means of Electrical Pin and pressure gauge techniques,an experimental study was made to explore the different mechanisms at work in the deflagration-detonation-transition(DDT) of three kinds of 40/60-TNT/RDX-composition B with different density in the range of 1.597 to 1.681g/cm~3.The experimental results showed that there was a critical density for transition to detonation at certain confinement condition.Different densities resulted in different results,transition to detonation was more easier for low density explosive.Under strong confinement condition(steel tube with an inner diameter of 20mm and an outer diameter of 64mm and length 500mm),a DDT was obtained for the composition B with density of 1.597g/cm~3,and the inducement distance was 295 to 310mm.