The Experts below are selected from a list of 129 Experts worldwide ranked by ideXlab platform
Saibal Mukhopadhyay - One of the best experts on this subject based on the ideXlab platform.
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reducing power side channel information leakage of aes Engines using fully integrated inductive voltage regulator
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper demonstrates an integrated inductive voltage regulator (IVR) for improving power side-channel-attack (PSCA) resistance of 128-bit Advanced Encryption Standard (AES-128) Engines. An inductive IVR is shown to transform the current signatures generated by an Encryption Engine. Furthermore, an all-digital circuit block, referred to as the loop-randomizer, is introduced to randomize the IVR transformations. A 130-nm test-chip with an inductive IVR with 11.6-nH inductance, 3.2-nF capacitance, and 125-MHz switching frequency is used to drive two different architectures of AES-128 Engine: high performance and low power. The measurements demonstrate that the IVR with loop randomizer eliminates information leakage while incurring only 3% overhead in performance and 5% overhead in power over a baseline IVR-AES system. Moreover, while a key-byte can be extracted for the standalone high-performance and low-power AES (LP-AES) with only 5000 and 1000 measurements, respectively, the proposed IVR inhibits key extraction even with 500 000 measurements.
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blindsight blinding em side channel leakage using built in fully integrated inductive voltage regulator
arXiv: Cryptography and Security, 2018Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu K Mathew, Santosh Ghosh, Raheem Beyah, Saibal MukhopadhyayAbstract:Modern high-performance as well as power-constrained System-on-Chips (SoC) are increasingly using hardware accelerated Encryption Engines to secure computation, memory access, and communication operations. The electromagnetic (EM) emission from a chip leaks information of the underlying logical operations and can be collected using low-cost non-invasive measurements. EM based side-channel attacks (EMSCA) have emerged as a major threat to security of Encryption Engines in a SoC. This paper presents the concept of Blindsight where a high-frequency inductive voltage regulator (IVR) integrated on the same chip with an Encryption Engine is used to increase resistance against EMSCA. High-frequency (~100MHz) IVRs are present in modern microprocessors to improve energy-efficiency. We show that an IVR with a randomized control loop (R-IVR) can reduce EMSCA as the integrated inductance acts as a strong EM emitter and blinds an adversary from EM emission of the Encryption Engine. The EM measurements are performed on a test-chip containing two architectures of a 128-bit Advanced Encryption Standard (AES) Engine powered by a high-frequency R-IVR and under two attack scenarios, one, where an adversary gains complete physical access of the target device and the other, where the adversary is only in proximity of the device. In both attack modes, an adversary can observe information leakage in Test Vector Leakage Assessment (TVLA) test in a baseline IVR (B-IVR, without control loop randomization). However, we show that EM emission from the R-IVR blinds the attacker and significantly reduces SCA vulnerability of the AES Engine. A range of practical side-channel analysis including TVLA, Correlation Electromagnetic Analysis (CEMA), and a template based CEMA shows that R-IVR can reduce information leakage and prevent key extraction even against a skilled adversary.
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what does ultra low power requirements mean for side channel secure cryptography
International Conference on Computer Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-attack resistant Encryption Engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel resistance. On one hand, low-power Encryption architecture can be more vulnerable to power-attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-attack resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
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exploiting fully integrated inductive voltage regulators to improve side channel resistance of Encryption Engines
International Symposium on Low Power Electronics and Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of Encryption Engines. We propose security aware design modes for low passive FIVR to improve robustness of an Encryption-Engine against statistical power attacks in time and frequency domain. A Correlation Power Analysis is used to attack a 128-bit AES Engine synthesized in 130nm CMOS. The original design requires ~250 Measurements to Disclose (MTD) the 1st byte of key; but with security-aware FIVR, the CPA was unsuccessful even after 20,000 traces. We present a reversibility based threat model for the FIVR-based protection improvement and show the robustness of security aware FIVR against such threat.
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exploring power attack protection of resource constrained Encryption Engines using integrated low drop out regulators
International Symposium on Low Power Electronics and Design, 2015Co-Authors: Arvind Singh, Monodeep Kar, Saibal MukhopadhyayAbstract:The power attack protection of Encryption Engines often comes at the expense of area, power, and/or performance overheads making the design of a low-power and compact but secure Encryption Engine challenging. This paper explores the feasibility of using an on-chip low dropout regulator (LDO) as a countermeasure to power attack of low-power and compact Encryption Engine. We design an area minimized implementation of Advanced Encryption Standard (AES) using predictive 45nm node and show that lightweight implementations are more susceptible to power attack. Using behavioral modeling, we show that an on-chip LDO can enhance power attack resistance of this compact AES Engine; however, the tradeoff between LDO performance and power attack protection is essential. Our analysis shows that LDO can increase power attack resistance of the compact AES by >800X with marginal area (1.4%) and power (5%) overheads.
Monodeep Kar - One of the best experts on this subject based on the ideXlab platform.
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reducing power side channel information leakage of aes Engines using fully integrated inductive voltage regulator
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper demonstrates an integrated inductive voltage regulator (IVR) for improving power side-channel-attack (PSCA) resistance of 128-bit Advanced Encryption Standard (AES-128) Engines. An inductive IVR is shown to transform the current signatures generated by an Encryption Engine. Furthermore, an all-digital circuit block, referred to as the loop-randomizer, is introduced to randomize the IVR transformations. A 130-nm test-chip with an inductive IVR with 11.6-nH inductance, 3.2-nF capacitance, and 125-MHz switching frequency is used to drive two different architectures of AES-128 Engine: high performance and low power. The measurements demonstrate that the IVR with loop randomizer eliminates information leakage while incurring only 3% overhead in performance and 5% overhead in power over a baseline IVR-AES system. Moreover, while a key-byte can be extracted for the standalone high-performance and low-power AES (LP-AES) with only 5000 and 1000 measurements, respectively, the proposed IVR inhibits key extraction even with 500 000 measurements.
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blindsight blinding em side channel leakage using built in fully integrated inductive voltage regulator
arXiv: Cryptography and Security, 2018Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu K Mathew, Santosh Ghosh, Raheem Beyah, Saibal MukhopadhyayAbstract:Modern high-performance as well as power-constrained System-on-Chips (SoC) are increasingly using hardware accelerated Encryption Engines to secure computation, memory access, and communication operations. The electromagnetic (EM) emission from a chip leaks information of the underlying logical operations and can be collected using low-cost non-invasive measurements. EM based side-channel attacks (EMSCA) have emerged as a major threat to security of Encryption Engines in a SoC. This paper presents the concept of Blindsight where a high-frequency inductive voltage regulator (IVR) integrated on the same chip with an Encryption Engine is used to increase resistance against EMSCA. High-frequency (~100MHz) IVRs are present in modern microprocessors to improve energy-efficiency. We show that an IVR with a randomized control loop (R-IVR) can reduce EMSCA as the integrated inductance acts as a strong EM emitter and blinds an adversary from EM emission of the Encryption Engine. The EM measurements are performed on a test-chip containing two architectures of a 128-bit Advanced Encryption Standard (AES) Engine powered by a high-frequency R-IVR and under two attack scenarios, one, where an adversary gains complete physical access of the target device and the other, where the adversary is only in proximity of the device. In both attack modes, an adversary can observe information leakage in Test Vector Leakage Assessment (TVLA) test in a baseline IVR (B-IVR, without control loop randomization). However, we show that EM emission from the R-IVR blinds the attacker and significantly reduces SCA vulnerability of the AES Engine. A range of practical side-channel analysis including TVLA, Correlation Electromagnetic Analysis (CEMA), and a template based CEMA shows that R-IVR can reduce information leakage and prevent key extraction even against a skilled adversary.
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what does ultra low power requirements mean for side channel secure cryptography
International Conference on Computer Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-attack resistant Encryption Engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel resistance. On one hand, low-power Encryption architecture can be more vulnerable to power-attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-attack resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
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exploiting fully integrated inductive voltage regulators to improve side channel resistance of Encryption Engines
International Symposium on Low Power Electronics and Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of Encryption Engines. We propose security aware design modes for low passive FIVR to improve robustness of an Encryption-Engine against statistical power attacks in time and frequency domain. A Correlation Power Analysis is used to attack a 128-bit AES Engine synthesized in 130nm CMOS. The original design requires ~250 Measurements to Disclose (MTD) the 1st byte of key; but with security-aware FIVR, the CPA was unsuccessful even after 20,000 traces. We present a reversibility based threat model for the FIVR-based protection improvement and show the robustness of security aware FIVR against such threat.
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exploring power attack protection of resource constrained Encryption Engines using integrated low drop out regulators
International Symposium on Low Power Electronics and Design, 2015Co-Authors: Arvind Singh, Monodeep Kar, Saibal MukhopadhyayAbstract:The power attack protection of Encryption Engines often comes at the expense of area, power, and/or performance overheads making the design of a low-power and compact but secure Encryption Engine challenging. This paper explores the feasibility of using an on-chip low dropout regulator (LDO) as a countermeasure to power attack of low-power and compact Encryption Engine. We design an area minimized implementation of Advanced Encryption Standard (AES) using predictive 45nm node and show that lightweight implementations are more susceptible to power attack. Using behavioral modeling, we show that an on-chip LDO can enhance power attack resistance of this compact AES Engine; however, the tradeoff between LDO performance and power attack protection is essential. Our analysis shows that LDO can increase power attack resistance of the compact AES by >800X with marginal area (1.4%) and power (5%) overheads.
Jiang Lei - One of the best experts on this subject based on the ideXlab platform.
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low cost reconstructable high speed Encryption Engine based on aes
Computer Engineering, 2008Co-Authors: Jiang LeiAbstract:This paper presents a solution of a high speed, low-cost and reconstructable Encryption Engine based on the AES Encryption aiming tosolve the balance problem of hardware resources and circuit performance in commercial Encryption Engines.According to FPGA inherent structuralfeatures, the four-level pipeline structure is improved and the Encryption module is described with VHDL.By expanding the password EncryptionEngine, the goal of real-time, reconstructability and security is achieved.Compared with some other Encryption Engines, this Encryption Engine has agood safety performance guarantee, speed and resources performance ratio.
Arvind Singh - One of the best experts on this subject based on the ideXlab platform.
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reducing power side channel information leakage of aes Engines using fully integrated inductive voltage regulator
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper demonstrates an integrated inductive voltage regulator (IVR) for improving power side-channel-attack (PSCA) resistance of 128-bit Advanced Encryption Standard (AES-128) Engines. An inductive IVR is shown to transform the current signatures generated by an Encryption Engine. Furthermore, an all-digital circuit block, referred to as the loop-randomizer, is introduced to randomize the IVR transformations. A 130-nm test-chip with an inductive IVR with 11.6-nH inductance, 3.2-nF capacitance, and 125-MHz switching frequency is used to drive two different architectures of AES-128 Engine: high performance and low power. The measurements demonstrate that the IVR with loop randomizer eliminates information leakage while incurring only 3% overhead in performance and 5% overhead in power over a baseline IVR-AES system. Moreover, while a key-byte can be extracted for the standalone high-performance and low-power AES (LP-AES) with only 5000 and 1000 measurements, respectively, the proposed IVR inhibits key extraction even with 500 000 measurements.
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blindsight blinding em side channel leakage using built in fully integrated inductive voltage regulator
arXiv: Cryptography and Security, 2018Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu K Mathew, Santosh Ghosh, Raheem Beyah, Saibal MukhopadhyayAbstract:Modern high-performance as well as power-constrained System-on-Chips (SoC) are increasingly using hardware accelerated Encryption Engines to secure computation, memory access, and communication operations. The electromagnetic (EM) emission from a chip leaks information of the underlying logical operations and can be collected using low-cost non-invasive measurements. EM based side-channel attacks (EMSCA) have emerged as a major threat to security of Encryption Engines in a SoC. This paper presents the concept of Blindsight where a high-frequency inductive voltage regulator (IVR) integrated on the same chip with an Encryption Engine is used to increase resistance against EMSCA. High-frequency (~100MHz) IVRs are present in modern microprocessors to improve energy-efficiency. We show that an IVR with a randomized control loop (R-IVR) can reduce EMSCA as the integrated inductance acts as a strong EM emitter and blinds an adversary from EM emission of the Encryption Engine. The EM measurements are performed on a test-chip containing two architectures of a 128-bit Advanced Encryption Standard (AES) Engine powered by a high-frequency R-IVR and under two attack scenarios, one, where an adversary gains complete physical access of the target device and the other, where the adversary is only in proximity of the device. In both attack modes, an adversary can observe information leakage in Test Vector Leakage Assessment (TVLA) test in a baseline IVR (B-IVR, without control loop randomization). However, we show that EM emission from the R-IVR blinds the attacker and significantly reduces SCA vulnerability of the AES Engine. A range of practical side-channel analysis including TVLA, Correlation Electromagnetic Analysis (CEMA), and a template based CEMA shows that R-IVR can reduce information leakage and prevent key extraction even against a skilled adversary.
-
what does ultra low power requirements mean for side channel secure cryptography
International Conference on Computer Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-attack resistant Encryption Engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel resistance. On one hand, low-power Encryption architecture can be more vulnerable to power-attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-attack resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
-
exploiting fully integrated inductive voltage regulators to improve side channel resistance of Encryption Engines
International Symposium on Low Power Electronics and Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of Encryption Engines. We propose security aware design modes for low passive FIVR to improve robustness of an Encryption-Engine against statistical power attacks in time and frequency domain. A Correlation Power Analysis is used to attack a 128-bit AES Engine synthesized in 130nm CMOS. The original design requires ~250 Measurements to Disclose (MTD) the 1st byte of key; but with security-aware FIVR, the CPA was unsuccessful even after 20,000 traces. We present a reversibility based threat model for the FIVR-based protection improvement and show the robustness of security aware FIVR against such threat.
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exploring power attack protection of resource constrained Encryption Engines using integrated low drop out regulators
International Symposium on Low Power Electronics and Design, 2015Co-Authors: Arvind Singh, Monodeep Kar, Saibal MukhopadhyayAbstract:The power attack protection of Encryption Engines often comes at the expense of area, power, and/or performance overheads making the design of a low-power and compact but secure Encryption Engine challenging. This paper explores the feasibility of using an on-chip low dropout regulator (LDO) as a countermeasure to power attack of low-power and compact Encryption Engine. We design an area minimized implementation of Advanced Encryption Standard (AES) using predictive 45nm node and show that lightweight implementations are more susceptible to power attack. Using behavioral modeling, we show that an on-chip LDO can enhance power attack resistance of this compact AES Engine; however, the tradeoff between LDO performance and power attack protection is essential. Our analysis shows that LDO can increase power attack resistance of the compact AES by >800X with marginal area (1.4%) and power (5%) overheads.
Anand Rajan - One of the best experts on this subject based on the ideXlab platform.
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reducing power side channel information leakage of aes Engines using fully integrated inductive voltage regulator
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper demonstrates an integrated inductive voltage regulator (IVR) for improving power side-channel-attack (PSCA) resistance of 128-bit Advanced Encryption Standard (AES-128) Engines. An inductive IVR is shown to transform the current signatures generated by an Encryption Engine. Furthermore, an all-digital circuit block, referred to as the loop-randomizer, is introduced to randomize the IVR transformations. A 130-nm test-chip with an inductive IVR with 11.6-nH inductance, 3.2-nF capacitance, and 125-MHz switching frequency is used to drive two different architectures of AES-128 Engine: high performance and low power. The measurements demonstrate that the IVR with loop randomizer eliminates information leakage while incurring only 3% overhead in performance and 5% overhead in power over a baseline IVR-AES system. Moreover, while a key-byte can be extracted for the standalone high-performance and low-power AES (LP-AES) with only 5000 and 1000 measurements, respectively, the proposed IVR inhibits key extraction even with 500 000 measurements.
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blindsight blinding em side channel leakage using built in fully integrated inductive voltage regulator
arXiv: Cryptography and Security, 2018Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu K Mathew, Santosh Ghosh, Raheem Beyah, Saibal MukhopadhyayAbstract:Modern high-performance as well as power-constrained System-on-Chips (SoC) are increasingly using hardware accelerated Encryption Engines to secure computation, memory access, and communication operations. The electromagnetic (EM) emission from a chip leaks information of the underlying logical operations and can be collected using low-cost non-invasive measurements. EM based side-channel attacks (EMSCA) have emerged as a major threat to security of Encryption Engines in a SoC. This paper presents the concept of Blindsight where a high-frequency inductive voltage regulator (IVR) integrated on the same chip with an Encryption Engine is used to increase resistance against EMSCA. High-frequency (~100MHz) IVRs are present in modern microprocessors to improve energy-efficiency. We show that an IVR with a randomized control loop (R-IVR) can reduce EMSCA as the integrated inductance acts as a strong EM emitter and blinds an adversary from EM emission of the Encryption Engine. The EM measurements are performed on a test-chip containing two architectures of a 128-bit Advanced Encryption Standard (AES) Engine powered by a high-frequency R-IVR and under two attack scenarios, one, where an adversary gains complete physical access of the target device and the other, where the adversary is only in proximity of the device. In both attack modes, an adversary can observe information leakage in Test Vector Leakage Assessment (TVLA) test in a baseline IVR (B-IVR, without control loop randomization). However, we show that EM emission from the R-IVR blinds the attacker and significantly reduces SCA vulnerability of the AES Engine. A range of practical side-channel analysis including TVLA, Correlation Electromagnetic Analysis (CEMA), and a template based CEMA shows that R-IVR can reduce information leakage and prevent key extraction even against a skilled adversary.
-
what does ultra low power requirements mean for side channel secure cryptography
International Conference on Computer Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-attack resistant Encryption Engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel resistance. On one hand, low-power Encryption architecture can be more vulnerable to power-attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-attack resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
-
exploiting fully integrated inductive voltage regulators to improve side channel resistance of Encryption Engines
International Symposium on Low Power Electronics and Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Arvind Singh, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of Encryption Engines. We propose security aware design modes for low passive FIVR to improve robustness of an Encryption-Engine against statistical power attacks in time and frequency domain. A Correlation Power Analysis is used to attack a 128-bit AES Engine synthesized in 130nm CMOS. The original design requires ~250 Measurements to Disclose (MTD) the 1st byte of key; but with security-aware FIVR, the CPA was unsuccessful even after 20,000 traces. We present a reversibility based threat model for the FIVR-based protection improvement and show the robustness of security aware FIVR against such threat.