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Sergio Bampi - One of the best experts on this subject based on the ideXlab platform.
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SBCCI - Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design Chip on the Sands - SBCCI '17, 2017Co-Authors: Camila De Matos Alonso, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Porto, Sergio BampiAbstract:The HEVC standard is one of the newest video coding standards developed to face the upcoming challenges concerning video processing. HEVC allows only one type of Entropy Encoder, which is the CABAC (Context Adaptive Binary Arithmetic Coding), responsible for the symbolic data representation in order to translate the final video bitstream to a smaller number of bits. This work presents hardware architecture for the binarization (Binarizer) block of CABAC, which is the first block in the Entropy encoding process, responsible for the data conversion to CABAC format. Therefore, this block aims to reduce the alphabet symbols size, thus simplifying the costs of context modeling and facilitating the task of the binary arithmetic coding. As a result of this work, low-power architecture with efficient performance was sought through statistical analysis of test video sequences for better low-power design suitability. Synthesis results show that the proposed low-power Binarizer architectures accomplished an average of around 20% of power savings (up to 41% for some cases) using real video sequences running on the gate-level netlist, and still fulfilled the performance constraints for 8K UHD video processing. The proposed work is the only one found on recent literature which focuses on low-power design for the Binarizer block.
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Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic Encoder architecture
2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI), 2017Co-Authors: Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio BampiAbstract:The HEVC is one of the most recent video coding standards, developed in order to face upcoming challenges, due to higher video quality and resolution. One of the HEVC components is the Entropy Encoder, which consists only of the Context Adaptive Binary Arithmetic Coding (CABAC) algorithm. The CABAC algorithm imposes some severe difficulties in order to achieve increasing throughput, due to the high data dependency among each processing element. Along with throughput, low-power consumption is a sought-after goal for video processing hardware architecture. This work proposes a novel multiplier-less scheme for multiple bypass bins processing focusing in increasing bin per cycle throughput focusing in low-power design for CABAC critical submodule Binary Arithmetic Encoder (BAE), with negligible degradation in frequency. The present work also accomplishes the insertion of low-power techniques, based on the average proportion of bins for video test sequences. Results show that the proposed work is able to process 8K UHD videos at 6.2 high tier with the minimum frequency among the works in the literature, which decreases the power dissipation of the block. The average power savings achieved by the insertion of low-power technique were, on average, 14.26%.
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Low-power HEVC Binarizer architecture for the CABAC block targeting UHD video processing
2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI), 2017Co-Authors: Camila De Matos Alonso, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Porto, Sergio BampiAbstract:The HEVC standard is one of the newest video coding standards developed to face the upcoming challenges concerning video processing. HEVC allows only one type of Entropy Encoder, which is the CABAC (Context Adaptive Binary Arithmetic Coding), responsible for the symbolic data representation in order to translate the final video bitstream to a smaller number of bits. This work presents hardware architecture for the binarization (Binarizer) block of CABAC, which is the first block in the Entropy encoding process, responsible for the data conversion to CABAC format. Therefore, this block aims to reduce the alphabet symbols size, thus simplifying the costs of context modeling and facilitating the task of the binary arithmetic coding. As a result of this work, low-power architecture with efficient performance was sought through statistical analysis of test video sequences for better low-power design suitability. Synthesis results show that the proposed low-power Binarizer architectures accomplished an average of around 20% of power savings (up to 41% for some cases) using real video sequences running on the gate-level netlist, and still fulfilled the performance constraints for 8K UHD video processing. The proposed work is the only one found on recent literature which focuses on low-power design for the Binarizer block.
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Area efficient and high throughput CABAC Encoder architecture for HEVC
2015 IEEE International Conference on Electronics Circuits and Systems (ICECS), 2015Co-Authors: Bruno Vizzotto, Volnei Mazui, Sergio BampiAbstract:The rising of High Efficiency Video Coding (HEVC) standard in the last years to encode Ultra High Definition (UHD) resolution videos bring challenges to both algorithmic and hardware solutions. The Entropy Encoder, Context-adaptive binary arithmetic coding (CABAC), presents difficulties to parallelize as well as pipelined with effectiveness. This occurs due to data dependencies in its algorithm. This paper presents an area efficient architecture to deliver the throughput required by CABAC encoding for UHD content. To meet this requirement, we propose optimizations in the renormalization exploiting parallelism, and, we improve the binary arithmetic encoding (BAE) by reducing the critical path delay while increasing the throughput. This technique increases the bins per clock cycle to an average of 2.37. Moreover, simulation results show that our architecture can work at 380MHz with 31.180K gates targeting 0.13μm CMOS process. These results endure support for real-time encoding for all sequences under common test conditions (CTC) of HEVC standard conforming to the main profile.
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Content-adaptive reference frame compression based on intra-frame prediction for multiview video coding
2013 IEEE International Conference on Image Processing, 2013Co-Authors: Felipe Sampaio, Bruno Zatt, Muhammad Shafique, Luciano Agostini, Jörg Henkel, Sergio BampiAbstract:This paper presents a content-adaptive reference frame compression scheme to alleviate the large overhead of external memory communication during the Motion and Disparity Estimation process in Multiview Video Coding (MVC). Our scheme is based on a simplified intra-prediction process to reduce the spatial redundancy of the reference samples. The intra-prediction residue is compressed by a path composed of non-linear quantization and Huffman-based Entropy Encoder. Four different quantization strengths and Huffman tables were statistically defined. They are dynamically selected according to a content adaptation strategy, which classifies the original blocks based on their spatial homogeneity. Experimental results show that the proposed content-adaptive compression scheme is able to reduce the external memory accesses by up to 63% along with negligible losses in the MVC Encoder rate-distortion performance. Compared to the best available related work [12] our content-adaptive reference frame compression achieves 39% reduced external memory accesses, while still providing a BD-PSNR increase of 0.03dB.
Min-chun Tuan - One of the best experts on this subject based on the ideXlab platform.
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VLSI Implementation of a Cost-Efficient Micro Control Unit With an Asymmetric Encryption for Wireless Body Sensor Networks
IEEE Access, 2017Co-Authors: Shih-lun Chen, Min-chun TuanAbstract:This paper presents a very large-scale integration (VLSI) circuit design of a micro control unit (MCU) for wireless body sensor networks (WBSNs) in cost-intention. The proposed MCU design consists of an asynchronous interface, a multisensor controller, a register bank, a hardware-shared filter, a lossless compressor, an encryption Encoder, an error correct coding (ECC) circuit, a universal asynchronous receiver/transmitter interface, a power management, and a QRS complex detector. A hardware-sharing technique was added to reduce the silicon area of a hardware-shared filter and provided functions in terms of high-pass, low-pass, and band-pass filters according to the uses of various body signals. The QRS complex detector was designed for calculating QRS information of the ECG signals. In addition, the QRS information is helpful to obtain the heart beats. The lossless compressor consists of an adaptive trending predictor and an extensible hybrid Entropy Encoder, which provides various methods to compress the different characteristics of body signals adaptively. Furthermore, an encryption Encoder based on an asymmetric cryptography technique was designed to protect the private physical information during wireless transmission. The proposed MCU design in this paper contained 7.61k gate counts and consumed 1.33 mW when operating at 200 MHz by using a 90-nm CMOS process. Compared with previous designs, this paper has the benefits of increasing the average compression rate by over 12% in ECG signal, providing body signals analysis, and enhancing security of the WBSNs.
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VLSI Implementation of a Cost-Efficient Near-Lossless CFA Image Compressor for Wireless Capsule Endoscopy
IEEE Access, 2016Co-Authors: Shih-lun Chen, Chia-wei Shen, Min-chun TuanAbstract:In this paper, a novel near-lossless color filter array (CFA) image compression algorithm based on JPEG-LS is proposed for VLSI implementation. It consists of a pixel restoration, a prediction, a run mode, and Entropy coding modules. According to the information of the previous research, a context table and row memory consumed more than 81% hardware cost in a JPEG-LS Encoder design. Hence, in this paper, a novel context-free and near-lossless image compression algorithm is presented. Since removing the context model causes decreasing of the compression performance, a novel prediction, run mode, and modified Golomb-Rice coding techniques were used to improve the compression efficiency. The VLSI architecture of the proposed image compressor consists of a register bank, a pixel restoration module, a predictor, a run mode module, and an Entropy Encoder. A pipeline technique was used to improve the performance of this. It contains only 10.9k gate count, and the core area is 30625 μm2 , synthesized by using a 90-nm CMOS process. Compared with the previous JPEG-LS designs, this paper reduces the gate counts by 44.1% and 41.7%, respectively, for five standard and eight endoscopy testing images in CFA format. It also improves the average PSNR values by 0.96 and 0.43 dB, respectively, for the same test images.
Shih-lun Chen - One of the best experts on this subject based on the ideXlab platform.
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VLSI Implementation of a Cost-Efficient Micro Control Unit With an Asymmetric Encryption for Wireless Body Sensor Networks
IEEE Access, 2017Co-Authors: Shih-lun Chen, Min-chun TuanAbstract:This paper presents a very large-scale integration (VLSI) circuit design of a micro control unit (MCU) for wireless body sensor networks (WBSNs) in cost-intention. The proposed MCU design consists of an asynchronous interface, a multisensor controller, a register bank, a hardware-shared filter, a lossless compressor, an encryption Encoder, an error correct coding (ECC) circuit, a universal asynchronous receiver/transmitter interface, a power management, and a QRS complex detector. A hardware-sharing technique was added to reduce the silicon area of a hardware-shared filter and provided functions in terms of high-pass, low-pass, and band-pass filters according to the uses of various body signals. The QRS complex detector was designed for calculating QRS information of the ECG signals. In addition, the QRS information is helpful to obtain the heart beats. The lossless compressor consists of an adaptive trending predictor and an extensible hybrid Entropy Encoder, which provides various methods to compress the different characteristics of body signals adaptively. Furthermore, an encryption Encoder based on an asymmetric cryptography technique was designed to protect the private physical information during wireless transmission. The proposed MCU design in this paper contained 7.61k gate counts and consumed 1.33 mW when operating at 200 MHz by using a 90-nm CMOS process. Compared with previous designs, this paper has the benefits of increasing the average compression rate by over 12% in ECG signal, providing body signals analysis, and enhancing security of the WBSNs.
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VLSI Implementation of a Cost-Efficient Near-Lossless CFA Image Compressor for Wireless Capsule Endoscopy
IEEE Access, 2016Co-Authors: Shih-lun Chen, Chia-wei Shen, Min-chun TuanAbstract:In this paper, a novel near-lossless color filter array (CFA) image compression algorithm based on JPEG-LS is proposed for VLSI implementation. It consists of a pixel restoration, a prediction, a run mode, and Entropy coding modules. According to the information of the previous research, a context table and row memory consumed more than 81% hardware cost in a JPEG-LS Encoder design. Hence, in this paper, a novel context-free and near-lossless image compression algorithm is presented. Since removing the context model causes decreasing of the compression performance, a novel prediction, run mode, and modified Golomb-Rice coding techniques were used to improve the compression efficiency. The VLSI architecture of the proposed image compressor consists of a register bank, a pixel restoration module, a predictor, a run mode module, and an Entropy Encoder. A pipeline technique was used to improve the performance of this. It contains only 10.9k gate count, and the core area is 30625 μm2 , synthesized by using a 90-nm CMOS process. Compared with the previous JPEG-LS designs, this paper reduces the gate counts by 44.1% and 41.7%, respectively, for five standard and eight endoscopy testing images in CFA format. It also improves the average PSNR values by 0.96 and 0.43 dB, respectively, for the same test images.
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VLSI implementation of a lossless ECG Encoder design with fuzzy decision and two-stage Huffman coding for wireless body sensor network
2013 9th International Conference on Information Communications & Signal Processing, 2013Co-Authors: Shih-lun ChenAbstract:An efficient VLSI design of lossless electrocardiogram (ECG) Encoder is proposed for wireless body sensor networks. To save wireless transmission power, a novel lossless encoding algorithm has been created for ECG signal compression. The proposed algorithm consists of an adaptive predictor based on the fuzzy decision control, and an Entropy Encoder including a two-stage Huffman coding. The VLSI architecture contains only 2.78 K gates and its core area is 34,411 μm2 synthesized by a 0.18 μm CMOS process. Moreover, this design can be operated at 100 MHz processing rate by consuming only 28.3 μW. It achieves an average compression rate of 2.53 for the MIT-BIH arrhythmia database. To compare with the previous low-complexity and high performance lossless ECG Encoder studies, it is performed higher compression rate, lower power consumption and lower hardware cost than VLSI design.
Xing Zhang - One of the best experts on this subject based on the ideXlab platform.
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Vlsi implementation of an Entropy Encoder for H.264/AVC baseline
2008 3rd IEEE Conference on Industrial Electronics and Applications, 2008Co-Authors: Weijun Lu, Ying Li, Dunshan Yu, Xing ZhangAbstract:In this paper, we implement a complete Entropy Encoder for H.264/AVC baseline profile composed of a CAVLC unit, an Exp-Golomb coding unit and a bit stream packer which can pack the bit stream in format of network abstraction layer (NAL). The Encoder is implemented with SYNOPSYS Design Compiler and SMIC 0.18 um cell library. The result shows that our design costs less area than the prior work in (Tung-Chien Chen, 2005) and it can work at frequency up to 200 MHZ. In the worst case, it takes 1905 circles to encode a macro block and can process 1844 QCIF (176 x 144) frames per second.
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vlsi implementation of an Entropy Encoder for h 264 avc baseline
Conference on Industrial Electronics and Applications, 2008Co-Authors: Weijun Lu, Ying Li, Dunshan Yu, Xing ZhangAbstract:In this paper, we implement a complete Entropy Encoder for H.264/AVC baseline profile composed of a CAVLC unit, an Exp-Golomb coding unit and a bit stream packer which can pack the bit stream in format of network abstraction layer (NAL). The Encoder is implemented with SYNOPSYS Design Compiler and SMIC 0.18 um cell library. The result shows that our design costs less area than the prior work in (Tung-Chien Chen, 2005) and it can work at frequency up to 200 MHZ. In the worst case, it takes 1905 circles to encode a macro block and can process 1844 QCIF (176 x 144) frames per second.
Markku Juntti - One of the best experts on this subject based on the ideXlab platform.
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Distributed Distortion-Rate Optimized Compressed Sensing in Wireless Sensor Networks
IEEE Transactions on Communications, 2018Co-Authors: Markus Leinonen, Marian Codreanu, Markku JunttiAbstract:This paper addresses lossy distributed source coding for acquiring correlated sparse sources via compressed sensing (CS) in wireless sensor networks. Noisy CS measurements are separately encoded at a finite rate by each sensor, followed by the joint reconstruction of the sources at the decoder. We develop a novel complexity-constrained distributed variable-rate quantized CS method, which minimizes a weighted sum between the mean square error signal reconstruction distortion and the average encoding rate. The encoding complexity of each sensor is restrained by pre-quantizing the Encoder input, i.e., the CS measurements, via vector quantization. Following the Entropy-constrained design, each Encoder is modeled as a quantizer followed by a lossless Entropy Encoder, and variable-rate coding is incorporated via rate measures of an Entropy bound. For a two-sensor system, necessary optimality conditions are derived, practical training algorithms are proposed, and complexity analysis is provided. Numerical results show that the proposed method achieves superior compression performance as compared with baseline methods, and lends itself to versatile setups with different performance requirements.