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S Mitra - One of the best experts on this subject based on the ideXlab platform.

  • verification guided soft Error Resilience
    Design Automation and Test in Europe, 2007
    Co-Authors: Sanjit A Seshia, Wenchao Li, S Mitra
    Abstract:

    Algorithmic techniques for formal verification can be used not just for bug-finding, but also to estimate vulnerability to reliability problems and to reduce overheads of circuit mechanisms for Error Resilience. We demonstrate this idea of verification-guided Error Resilience in the context of soft Errors in latches. We show how model checking can be used to identify latches in a circuit that must be protected in order that the circuit satisfies a formal specification. Experimental results on a Verilog implementation of the ESA SpaceWire communication protocol indicate that the power overhead of soft Error protection can be reduced by a factor of 4.35 by using our approach rather than protecting all latches.

  • DATE - Verification-guided soft Error Resilience
    2007 Design Automation & Test in Europe Conference & Exhibition, 2007
    Co-Authors: Sanjit A Seshia, Wenchao Li, S Mitra
    Abstract:

    Algorithmic techniques for formal verification can be used not just for bug-finding, but also to estimate vulnerability to reliability problems and to reduce overheads of circuit mechanisms for Error Resilience. We demonstrate this idea of verification-guided Error Resilience in the context of soft Errors in latches. We show how model checking can be used to identify latches in a circuit that must be protected in order that the circuit satisfies a formal specification. Experimental results on a Verilog implementation of the ESA SpaceWire communication protocol indicate that the power overhead of soft Error protection can be reduced by a factor of 4.35 by using our approach rather than protecting all latches.

  • Verication-Guided Soft Error Resilience
    2007
    Co-Authors: Sanjit A Seshia, Wenchao Li, S Mitra
    Abstract:

    Algorithmic techniques for formal verication can be used not just for bug-nding , but also to estimate vulnerability to reliability problems and to reduce overheads of circuit mechanisms for Error Resilience. We demonstrate this idea of verication-guide d Error Resilience in the context of soft Errors in latches. We show how model checking can be used to identify latches in a circuit that must be protected in order that the circuit satises a formal specication. Experimental results on a Verilog implementation of the ESA SpaceWire communication protocol indicate that the power overhead of soft Error protection can be reduced by a factor of 4.35 by using our approach rather than protecting all latches.

  • IOLTS - DFT assisted built-in soft Error Resilience
    11th IEEE International On-Line Testing Symposium, 2005
    Co-Authors: S Mitra, Ming Zhang
    Abstract:

    In this talk, we describe a new paradigm to design in soft Error Resilience by reusing already existent on-chip DFT resources. For example, scan systems that are required for manufacturing test and debug involve significant circuitry that are used only during post-silicon debug and production testing. These resources are then left unused throughout the entire lifetime of the product as they are not required for normal system operation. These structures continue to occupy additional silicon area and draw additional leakage power. We demonstrate how to reuse these scan resources to enable a built-in soft Error Resilience (BISER) design paradigm. These circuits result in more than 20 times reduction in soft Error rate while incurring a system-level power overhead of 3-5%. Additional power-saving techniques are possible. The BISER techniques produce the best results in terms of power, performance and area overheads (when all 3 attributes are considered) compared to traditional major redundancy techniques. These techniques are also suitable for adaptive applications targeting a wide range of applications (e.g., networking ASICs, microprocessors) with various power, performance and soft Error rate trade-offs.

Jeremie Lecomte - One of the best experts on this subject based on the ideXlab platform.

  • improved Error Resilience for volte and voip with 3gpp evs channel aware coding
    International Conference on Acoustics Speech and Signal Processing, 2015
    Co-Authors: Venkatraman Atti, Daniel J Sinder, Shaminda Subasingha, Vivek Rajendran, Duminda Dewasurendra, Venkata Subrahmanyam Chandra Sekhar Chebiyyam, Imre Varga, Venkatesh Krishnan, Benjamin Schubert, Jeremie Lecomte
    Abstract:

    A highly Error resilient mode of the newly standardized 3GPP EVS speech codec is described. Compared to the AMR-WB codec and other conversational codecs, the EVS channel aware mode offers significantly improved Error Resilience in voice communication over packet-switched networks such as Voice-over-IP (VoIP) and Voice-over-LTE (VoLTE). The Error Resilience is achieved using a form of in-band forward Error correction. Source-controlled coding techniques are used to identify candidate speech frames for bitrate reduction, leaving spare bits for transmission of partial copies of prior frames such that a constant bit rate is maintained. The self-contained partial copies are used to improve the Error robustness in case the original primary frame is lost or discarded due to late arrival. Subjective evaluation results from ITU-T P.800 Mean Opinion Score (MOS) tests are provided, showing improved quality under channel impairments as well as negligible impact to clean channel performance.

  • ICASSP - Improved Error Resilience for volte and VoIP with 3GPP EVS channel aware coding
    2015 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), 2015
    Co-Authors: Venkatraman Atti, Daniel J Sinder, Shaminda Subasingha, Vivek Rajendran, Duminda Dewasurendra, Venkata Subrahmanyam Chandra Sekhar Chebiyyam, Imre Varga, Venkatesh Krishnan, Benjamin Schubert, Jeremie Lecomte
    Abstract:

    A highly Error resilient mode of the newly standardized 3GPP EVS speech codec is described. Compared to the AMR-WB codec and other conversational codecs, the EVS channel aware mode offers significantly improved Error Resilience in voice communication over packet-switched networks such as Voice-over-IP (VoIP) and Voice-over-LTE (VoLTE). The Error Resilience is achieved using a form of in-band forward Error correction. Source-controlled coding techniques are used to identify candidate speech frames for bitrate reduction, leaving spare bits for transmission of partial copies of prior frames such that a constant bit rate is maintained. The self-contained partial copies are used to improve the Error robustness in case the original primary frame is lost or discarded due to late arrival. Subjective evaluation results from ITU-T P.800 Mean Opinion Score (MOS) tests are provided, showing improved quality under channel impairments as well as negligible impact to clean channel performance.

Yin Zhang - One of the best experts on this subject based on the ideXlab platform.

  • H.264/SVC Error Resilience strategies for 3G video service
    2009 International Conference on Image Analysis and Signal Processing, 2009
    Co-Authors: Sanyuan Zhang, Shuchang Xu, Yin Zhang
    Abstract:

    Scalable Video Codec (SVC) is an extension to the H.264/AVC that provides support for different types of scalability. 3GPP video services (e.g. Multimedia Broadcast/Multicast Services, Packet-switched Streaming Service and Conversational Service etc.) may greatly benefit from the adoption of SVC. The latest 3GPP/3GPP2 standards have already begun to support for H.264/SVC. Due to high packet loss rate in wireless environment, Error Resilience is still a challenge for H.264/SVC and Error Resilience tools of H.264/SVC are different from H.264/AVC. In this paper, we analyze the various Error Resilience tools of H.264/SVC and their functions and present two Error Resilience strategies for Multimedia Broadcast/Multicast Services and Conversational Service respectively. We test the proposed strategies by using the off-line common test conditions. Our experiments show that the proposed strategies can achieve satisfactory results.

  • Error Resilience schemes of h 264 avc for 3g conversational video services
    Computer and Information Technology, 2005
    Co-Authors: Sanyuan Zhang, Xiuzi Ye, Yin Zhang
    Abstract:

    The emerging of third generation mobile system (3G) makes conversational video transmission in wireless environment possible, and the latest 3GPP/3GPP2 standards suggest 3G terminals support H.264/AVC. Due to high bit Error rate in wireless environment, Error Resilience schemes are necessary for 3G terminals. Moreover, according to 3GPP/3GPP2, 3G terminals support only part of Error Resilience tools of H.264/AVC. This paper lists various Error Resilience tools and analyzes their usability in 3G environment, and at the same time, some Error Resilience schemes are proposed. Performances of these Error Resilience schemes are tested using offline common test conditions. Experiments shows that, in 3G environment, encoding with simple FMO mode and extra intra block refreshing can achieve the best Error correction ability, because this method can make full use of spatial correlation for intra predication and reduce the requirement of bit rate.

  • CIT - Error Resilience schemes of H.264/AVC for 3G conversational video services
    The Fifth International Conference on Computer and Information Technology (CIT'05), 2005
    Co-Authors: Sanyuan Zhang, Xiuzi Ye, Yin Zhang
    Abstract:

    The emerging of third generation mobile system (3G) makes conversational video transmission in wireless environment possible, and the latest 3GPP/3GPP2 standards suggest 3G terminals support H.264/AVC. Due to high bit Error rate in wireless environment, Error Resilience schemes are necessary for 3G terminals. Moreover, according to 3GPP/3GPP2, 3G terminals support only part of Error Resilience tools of H.264/AVC. This paper lists various Error Resilience tools and analyzes their usability in 3G environment, and at the same time, some Error Resilience schemes are proposed. Performances of these Error Resilience schemes are tested using offline common test conditions. Experiments shows that, in 3G environment, encoding with simple FMO mode and extra intra block refreshing can achieve the best Error correction ability, because this method can make full use of spatial correlation for intra predication and reduce the requirement of bit rate.

  • h 264 avc Error Resilience tools suitable for 3g mobile video services
    Journal of Zhejiang University Science, 2005
    Co-Authors: Xiuzi Ye, Sanyuan Zhang, Yin Zhang
    Abstract:

    The emergence of third generation mobile system (3G) makes video transmission in wireless environment possible, and the latest 3GPP/3GPP2 standards require 3G terminals support H.264/AVC. Due to high packet loss rate in wireless envi- ronment, Error Resilience for 3G terminals is necessary. Moreover, because of the hardware restrictions, 3G mobile terminals support only part of H.264/AVC Error Resilience tool. This paper analyzes various Error Resilience tools and their functions, and presents 2 Error Resilience strategies for 3G mobile streaming video services and mobile conversational services. Performances of the proposed Error Resilience strategies were tested using off-line common test conditions. Experiments showed that the proposed Error Resilience strategies can yield reasonably satisfactory results.

  • H.264/AVC Error Resilience tools suitable for 3G mobile video services *
    Journal of Zhejiang University Science, 2005
    Co-Authors: Xiuzi Ye, Sanyuan Zhang, Yin Zhang
    Abstract:

    The emergence of third generation mobile system (3G) makes video transmission in wireless environment possible, and the latest 3GPP/3GPP2 standards require 3G terminals support H.264/AVC. Due to high packet loss rate in wireless envi- ronment, Error Resilience for 3G terminals is necessary. Moreover, because of the hardware restrictions, 3G mobile terminals support only part of H.264/AVC Error Resilience tool. This paper analyzes various Error Resilience tools and their functions, and presents 2 Error Resilience strategies for 3G mobile streaming video services and mobile conversational services. Performances of the proposed Error Resilience strategies were tested using off-line common test conditions. Experiments showed that the proposed Error Resilience strategies can yield reasonably satisfactory results.

Jorg Henkel - One of the best experts on this subject based on the ideXlab platform.

  • aser adaptive soft Error Resilience for reliability heterogeneous processors in the dark silicon era
    Design Automation Conference, 2014
    Co-Authors: Florian Kriebel, Semeen Rehman, Muhammad Shafique, Jorg Henkel
    Abstract:

    The Dark Silicon provides opportunities to realize Reliability-Heterogeneous Processors with ISA compatible cores having different levels of protection against reliability threats (like soft Errors). This paper presents design-time customization of Reliability-Heterogeneous Processors given a set of applications and area constraints. A run-time system adaptively manages the soft Error Resilience under a given thermal design power (TDP) budget. We synthesize an embedded processor with different levels of protection and present area and power results for a 45nm technology. We illustrate the benefits of adaptive soft Error Resilience by comparing it with four different state-of-the-art approaches where we achieve 58%-96% overall system reliability improvements under a tight TDP constraint (corresponding to a 65% dark area).

  • DAC - ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era
    Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14, 2014
    Co-Authors: Florian Kriebel, Semeen Rehman, Muhammad Shafique, Jorg Henkel
    Abstract:

    The Dark Silicon provides opportunities to realize Reliability-Heterogeneous Processors with ISA compatible cores having different levels of protection against reliability threats (like soft Errors). This paper presents design-time customization of Reliability-Heterogeneous Processors given a set of applications and area constraints. A run-time system adaptively manages the soft Error Resilience under a given thermal design power (TDP) budget. We synthesize an embedded processor with different levels of protection and present area and power results for a 45nm technology. We illustrate the benefits of adaptive soft Error Resilience by comparing it with four different state-of-the-art approaches where we achieve 58%-96% overall system reliability improvements under a tight TDP constraint (corresponding to a 65% dark area).

Sanjit A Seshia - One of the best experts on this subject based on the ideXlab platform.

  • verification guided soft Error Resilience
    Design Automation and Test in Europe, 2007
    Co-Authors: Sanjit A Seshia, Wenchao Li, S Mitra
    Abstract:

    Algorithmic techniques for formal verification can be used not just for bug-finding, but also to estimate vulnerability to reliability problems and to reduce overheads of circuit mechanisms for Error Resilience. We demonstrate this idea of verification-guided Error Resilience in the context of soft Errors in latches. We show how model checking can be used to identify latches in a circuit that must be protected in order that the circuit satisfies a formal specification. Experimental results on a Verilog implementation of the ESA SpaceWire communication protocol indicate that the power overhead of soft Error protection can be reduced by a factor of 4.35 by using our approach rather than protecting all latches.

  • DATE - Verification-guided soft Error Resilience
    2007 Design Automation & Test in Europe Conference & Exhibition, 2007
    Co-Authors: Sanjit A Seshia, Wenchao Li, S Mitra
    Abstract:

    Algorithmic techniques for formal verification can be used not just for bug-finding, but also to estimate vulnerability to reliability problems and to reduce overheads of circuit mechanisms for Error Resilience. We demonstrate this idea of verification-guided Error Resilience in the context of soft Errors in latches. We show how model checking can be used to identify latches in a circuit that must be protected in order that the circuit satisfies a formal specification. Experimental results on a Verilog implementation of the ESA SpaceWire communication protocol indicate that the power overhead of soft Error protection can be reduced by a factor of 4.35 by using our approach rather than protecting all latches.

  • Verication-Guided Soft Error Resilience
    2007
    Co-Authors: Sanjit A Seshia, Wenchao Li, S Mitra
    Abstract:

    Algorithmic techniques for formal verication can be used not just for bug-nding , but also to estimate vulnerability to reliability problems and to reduce overheads of circuit mechanisms for Error Resilience. We demonstrate this idea of verication-guide d Error Resilience in the context of soft Errors in latches. We show how model checking can be used to identify latches in a circuit that must be protected in order that the circuit satises a formal specication. Experimental results on a Verilog implementation of the ESA SpaceWire communication protocol indicate that the power overhead of soft Error protection can be reduced by a factor of 4.35 by using our approach rather than protecting all latches.