The Experts below are selected from a list of 174 Experts worldwide ranked by ideXlab platform
Takashi Yoshikawa - One of the best experts on this subject based on the ideXlab platform.
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Hot Interconnects - End-to-End Adaptive Packet Aggregation for High-Throughput I/O Bus Network Using Ethernet
2014 IEEE 22nd Annual Symposium on High-Performance Interconnects, 2014Co-Authors: Jun Suzuki, Yuki Hayashi, Shinya Miyakawa, Takashi YoshikawaAbstract:Input/output (I/O) bus networks using Ethernets transfer a PCI Express (PCIe) I/O packet between a host and an I/O device by encapsulating it into an Ethernet frame. Because the size of PCIe packets is generally small in such systems, the overhead to individually encapsulate them into Ethernet frames lowers the PCIe throughput provided by Ethernet connections. This decrease in throughput directly degrades the performance of I/O devices, which transmit high-throughput PCIe traffic. Examples of such devices include PCIe solid-state drives and graphics processing units. We propose a method of aggregating multiple PCIe packets into a single Ethernet frame in an end-to-end manner to provide a high-throughput PCIe connection. The aggregation is performed at the bottleneck-link rate of the Ethernet path through which those packets are transferred. The number of aggregated PCIe packets is adaptively determined by aggregating ones that reside in a transmission queue when it is scheduled to transmit packets. This enables low-latency throughput enhancement because the proposed method does not increase the transmission latency of PCIe packets by waiting for more packets to aggregate. In addition, it does not require individual configuration of operation parameters, such as aggregation threshold and time out value, depending on the rate of the PCIe traffic of I/O devices. We implemented our method in a PCIe-to-Ethernet Bridge prototype using a field-programmable gate array. As a result, I/O performance improved up to 41%.
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End-to-End Adaptive Packet Aggregation for High-Throughput I/O Bus Network Using Ethernet
2014 IEEE 22nd Annual Symposium on High-Performance Interconnects, 2014Co-Authors: Jun Suzuki, Yuki Hayashi, Shinya Miyakawa, Takashi YoshikawaAbstract:Input/output (I/O) bus networks using Ethernets transfer a PCI Express (PCIe) I/O packet between a host and an I/O device by encapsulating it into an Ethernet frame. Because the size of PCIe packets is generally small in such systems, the overhead to individually encapsulate them into Ethernet frames lowers the PCIe throughput provided by Ethernet connections. This decrease in throughput directly degrades the performance of I/O devices, which transmit high-throughput PCIe traffic. Examples of such devices include PCIe solid-state drives and graphics processing units. We propose a method of aggregating multiple PCIe packets into a single Ethernet frame in an end-to-end manner to provide a high-throughput PCIe connection. The aggregation is performed at the bottleneck-link rate of the Ethernet path through which those packets are transferred. The number of aggregated PCIe packets is adaptively determined by aggregating ones that reside in a transmission queue when it is scheduled to transmit packets. This enables low-latency throughput enhancement because the proposed method does not increase the transmission latency of PCIe packets by waiting for more packets to aggregate. In addition, it does not require individual configuration of operation parameters, such as aggregation threshold and time out value, depending on the rate of the PCIe traffic of I/O devices. We implemented our method in a PCIe-to-Ethernet Bridge prototype using a field-programmable gate array. As a result, I/O performance improved up to 41%.
Upena D. Dalal - One of the best experts on this subject based on the ideXlab platform.
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Kaleidoscope - Performance comparison of Intelligent Jamming in RF (Physical) Layer with WLAN Ethernet Router and WLAN Ethernet Bridge
2010Co-Authors: Upena D. DalalAbstract:The very nature of Radio Frequency (RF) technology makes Wireless LANs (WLANs) open to a variety of unique attacks. Most of these RF-related attacks begin as exploits of Layer 1 (Physical — PHY) & Layer 2 (Media Access Control — MAC) of the 802.11 specification, and then build into a wide array of more advanced assaults, including Denial of Service (DOS) attacks. In Intelligent Jamming the jammer jammed physical layer of WLAN by generating continuous high power noise in the vicinity of wireless receiver nodes. In this paper, we study the threats in an Intelligent jamming Comparison with WLAN Ethernet Router and WLAN Ethernet Bridge and the security goals to be achieved. We present and examine analytical simulation results for the throughput for different scenario performance, using the well-known network simulator OPNET 10.0 and OPNET Modeler 14.5 for WiMAX Performance. IEEE 802.11b has two different DCF modes: basic CSMA/CA and RTS/CTS. Intelligent jamming, which jams with the knowledge of the protocol, the jamming describe in our paper is based on the basis of Fake AP Jamming. When we have applied same concept in WiMAX system under the influence of jamming we have received same effect of router performance.
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Performance comparison of Intelligent Jamming in RF (Physical) Layer with WLAN Ethernet Router and WLAN Ethernet Bridge
2010 ITU-T Kaleidoscope: Beyond the Internet? - Innovations for Future Networks and Services, 2010Co-Authors: R.k. Jha, Upena D. DalalAbstract:The very nature of Radio Frequency (RF) technology makes Wireless LANs (WLANs) open to a variety of unique attacks. Most of these RF-related attacks begin as exploits of Layer 1 (Physical - PHY) & Layer 2 (Media Access Control - MAC) of the 802.11 specification, and then build into a wide array of more advanced assaults, including Denial of Service (DOS) attacks. In Intelligent Jamming the jammer jammed physical layer of WLAN by generating continuous high power noise in the vicinity of wireless receiver nodes. In this paper, we study the threats in an Intelligent jamming Comparison with WLAN Ethernet Router and WLAN Ethernet Bridge and the security goals to be achieved. We present and examine analytical simulation results for the throughput for different scenario performance, using the well-known network simulator OPNET 10.0 and OPNET Modeler 14.5 for WiMAX Performance. IEEE 802.11b has two different DCF modes: basic CSMA/CA and RTS/CTS. Intelligent jamming, which jams with the knowledge of the protocol, the jamming describe in our paper is based on the basis of Fake AP Jamming. When we have applied same concept in WiMAX system under the influence of jamming we have received same effect of router performance.
Jason L. Wright - One of the best experts on this subject based on the ideXlab platform.
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USENIX Annual Technical Conference, FREENIX Track - Transparent network security policy enforcement
2000Co-Authors: Angelos D Keromytis, Jason L. WrightAbstract:Recent work in the area of network security, such as IPsec, provides mechanisms for securing the traffic between any two interconnected hosts. However, it is not always possible, economical, or even practical from an administration and operational point of view to upgrade the software and configuration of all the nodes in a network to support such security protocols. One apparent solution to this problem is the use of security gateways that apply the relevant security protocols on behalf of the protected nodes, under the assumption that the "last hop" between the security gateway and the end node is safe without cryptography. Such a gateway can be set to enforce specific security policies for different types of traffic. While this solution is appealing in static scenarios (such as building so-called "intranets"), the use of Layer-3 (network) routers as security gateways presents some transparency and configuration problems with regards to peer authentication in the automated key management protocol. This paper describes the architecture and implementation of a Layer-2 (link layer) Bridge with extensions for offering Layer-3 security services. We extend the OpenBSD Ethernet Bridge to perform simple IP packet filtering and IPsec processing for incoming and outgoing packets on behalf of a protected node, completely transparently to both the protected and the remote communication endpoint. The same mechanism may be used to construct "virtual local area networks," by establishing IPsec tunnels between OpenBSD Bridges connected geographically separated LANs. As our system operates in the link layer, there is no need for software or configuration changes in the protected nodes.
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Transparent Network Security Policy Enforcement
Freenix, 2000Co-Authors: Angelos D Keromytis, Jason L. WrightAbstract:Recent work in the area of network security, such as IPsec,\nprovides mechanisms for securing the traffic between any two\ninterconnected hosts. However, it is not always possible, economical, or\neven practical from an administration and operational point of view to\nupgrade the software and configuration of all the nodes in a network to\nsupport such security protocols. One apparent solution to this problem\nis the use of security gateways that apply the relevant security\nprotocols on behalf of the protected nodes, under the assumption that\nthe ``last hop'' between the security gateway and the end node is safe\nwithout cryptography. Such a gateway can be set to enforce specific\nsecurity policies for different types of traffic. While this solution is\nappealing in static scenarios (such as building so-called\n``intranets''), the use of Layer-3 (network) routers as security\ngateways presents some transparency and configuration problems with\nregards to peer authentication in the automated key management protocol.\nThis paper describes the architecture and implementation of a Layer-2\n(link layer) Bridge with extensions for offering Layer-3 security\nservices. We extend the OpenBSD Ethernet Bridge to perform simple IP\npacket filtering and IPsec processing for incoming and outgoing packets\non behalf of a protected node, completely transparently to both the\nprotected and the remote communication endpoint. The same mechanism may\nbe used to construct ``virtual local area networks,'' by establishing\nIPsec tunnels between OpenBSD Bridges connected geographically separated\nLANs. As our system operates in the link layer, there is no need for\nsoftware or configuration changes in the protected nodes.
Xing-xi Chen - One of the best experts on this subject based on the ideXlab platform.
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SMC - Packet Process with Deficit Round Robin ASIC for ATM/Ethernet Bridge
2015 IEEE International Conference on Systems Man and Cybernetics, 2015Co-Authors: Guo-ming Sung, Wen-duen Chou, Xing-xi ChenAbstract:This paper presents a packet process with deficit round robin (DRR) ASIC, which is used not only to give up the first-in first-out (FIFO) mechanism in ATM/Ethernet Bridge, but also to integrate with UTOPIA (Universal Test and Operations PHY Interface for ATM) interface between ATM Cell and Ethernet packet. Usually, the packet presents with different weight in the DRR queue. The higher the weight is, the higher the priority is to transmit packet. The proposed DRR ASIC completes the packet process with low delay and low loss. The Alter a DE3 of FPGA (Field Programmable Gate Array) is adopted to verify the designed function, and that the TSMC 0.18µm CMOS technology is used to implement the DRR ASIC after completing the design process, which includes the Synthesis, DFT (Design For Testability), APR (Auto Place and Route) DRC (Design Rule Check) and LVS (Layout Versus Schematic). According to the simulation results, the proposed ASIC performs with the gate count of 31,948 and the power consumption of 8.48 mW.
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packet process with deficit round robin asic for atm Ethernet Bridge
Systems Man and Cybernetics, 2015Co-Authors: Guo-ming Sung, Wen-duen Chou, Xing-xi ChenAbstract:This paper presents a packet process with deficit round robin (DRR) ASIC, which is used not only to give up the first-in first-out (FIFO) mechanism in ATM/Ethernet Bridge, but also to integrate with UTOPIA (Universal Test and Operations PHY Interface for ATM) interface between ATM Cell and Ethernet packet. Usually, the packet presents with different weight in the DRR queue. The higher the weight is, the higher the priority is to transmit packet. The proposed DRR ASIC completes the packet process with low delay and low loss. The Alter a DE3 of FPGA (Field Programmable Gate Array) is adopted to verify the designed function, and that the TSMC 0.18µm CMOS technology is used to implement the DRR ASIC after completing the design process, which includes the Synthesis, DFT (Design For Testability), APR (Auto Place and Route) DRC (Design Rule Check) and LVS (Layout Versus Schematic). According to the simulation results, the proposed ASIC performs with the gate count of 31,948 and the power consumption of 8.48 mW.
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Packet Process with Deficit Round Robin ASIC for ATM/Ethernet Bridge
2015 IEEE International Conference on Systems Man and Cybernetics, 2015Co-Authors: Guo-ming Sung, Wen-duen Chou, Xing-xi ChenAbstract:This paper presents a packet process with deficit round robin (DRR) ASIC, which is used not only to give up the first-in first-out (FIFO) mechanism in ATM/Ethernet Bridge, but also to integrate with UTOPIA (Universal Test and Operations PHY Interface for ATM) interface between ATM Cell and Ethernet packet. Usually, the packet presents with different weight in the DRR queue. The higher the weight is, the higher the priority is to transmit packet. The proposed DRR ASIC completes the packet process with low delay and low loss. The Alter a DE3 of FPGA (Field Programmable Gate Array) is adopted to verify the designed function, and that the TSMC 0.18μm CMOS technology is used to implement the DRR ASIC after completing the design process, which includes the Synthesis, DFT (Design For Testability), APR (Auto Place and Route) DRC (Design Rule Check) and LVS (Layout Versus Schematic). According to the simulation results, the proposed ASIC performs with the gate count of 31,948 and the power consumption of 8.48 mW.
Guo-ming Sung - One of the best experts on this subject based on the ideXlab platform.
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packet process with deficit round robin asic for atm Ethernet Bridge
Systems Man and Cybernetics, 2015Co-Authors: Guo-ming Sung, Wen-duen Chou, Xing-xi ChenAbstract:This paper presents a packet process with deficit round robin (DRR) ASIC, which is used not only to give up the first-in first-out (FIFO) mechanism in ATM/Ethernet Bridge, but also to integrate with UTOPIA (Universal Test and Operations PHY Interface for ATM) interface between ATM Cell and Ethernet packet. Usually, the packet presents with different weight in the DRR queue. The higher the weight is, the higher the priority is to transmit packet. The proposed DRR ASIC completes the packet process with low delay and low loss. The Alter a DE3 of FPGA (Field Programmable Gate Array) is adopted to verify the designed function, and that the TSMC 0.18µm CMOS technology is used to implement the DRR ASIC after completing the design process, which includes the Synthesis, DFT (Design For Testability), APR (Auto Place and Route) DRC (Design Rule Check) and LVS (Layout Versus Schematic). According to the simulation results, the proposed ASIC performs with the gate count of 31,948 and the power consumption of 8.48 mW.
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SMC - Packet Process with Deficit Round Robin ASIC for ATM/Ethernet Bridge
2015 IEEE International Conference on Systems Man and Cybernetics, 2015Co-Authors: Guo-ming Sung, Wen-duen Chou, Xing-xi ChenAbstract:This paper presents a packet process with deficit round robin (DRR) ASIC, which is used not only to give up the first-in first-out (FIFO) mechanism in ATM/Ethernet Bridge, but also to integrate with UTOPIA (Universal Test and Operations PHY Interface for ATM) interface between ATM Cell and Ethernet packet. Usually, the packet presents with different weight in the DRR queue. The higher the weight is, the higher the priority is to transmit packet. The proposed DRR ASIC completes the packet process with low delay and low loss. The Alter a DE3 of FPGA (Field Programmable Gate Array) is adopted to verify the designed function, and that the TSMC 0.18µm CMOS technology is used to implement the DRR ASIC after completing the design process, which includes the Synthesis, DFT (Design For Testability), APR (Auto Place and Route) DRC (Design Rule Check) and LVS (Layout Versus Schematic). According to the simulation results, the proposed ASIC performs with the gate count of 31,948 and the power consumption of 8.48 mW.
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Packet Process with Deficit Round Robin ASIC for ATM/Ethernet Bridge
2015 IEEE International Conference on Systems Man and Cybernetics, 2015Co-Authors: Guo-ming Sung, Wen-duen Chou, Xing-xi ChenAbstract:This paper presents a packet process with deficit round robin (DRR) ASIC, which is used not only to give up the first-in first-out (FIFO) mechanism in ATM/Ethernet Bridge, but also to integrate with UTOPIA (Universal Test and Operations PHY Interface for ATM) interface between ATM Cell and Ethernet packet. Usually, the packet presents with different weight in the DRR queue. The higher the weight is, the higher the priority is to transmit packet. The proposed DRR ASIC completes the packet process with low delay and low loss. The Alter a DE3 of FPGA (Field Programmable Gate Array) is adopted to verify the designed function, and that the TSMC 0.18μm CMOS technology is used to implement the DRR ASIC after completing the design process, which includes the Synthesis, DFT (Design For Testability), APR (Auto Place and Route) DRC (Design Rule Check) and LVS (Layout Versus Schematic). According to the simulation results, the proposed ASIC performs with the gate count of 31,948 and the power consumption of 8.48 mW.
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High speed deficit round robin ASIC in ATM/Ethernet Bridge
2014 IEEE International Conference on Systems Man and Cybernetics (SMC), 2014Co-Authors: Guo-ming Sung, Wen-duen Chou, Wen-shiou HoAbstract:This paper presents a deficit round robin (DRR) application specific integrated circuit (ASIC), which is fabricated in a standard TSMC 0.18μm 1P6M technology. The proposed DRR ASIC not only replaces the first-in-first-out (FIFO) queue with DRR, but also improves the performance of ATM/Ethernet Bridge with a fair queue in very-high-bit-rate digital subscriber line (VDSL). In the proposed DRR queue, two data formats, 4-bit and 8-bit widths, are studied. Notify that the average waiting time increases if the input queue works with small data format. According to the simulation result, the proposed DRR ASIC performs with the fault coverage of 99.5 % and the logic elements of 5,978 at the operating frequency of 50 MHz, the supplied voltage of 1.8 V and the power consumption of 90.1 mW; and that the chip area of the proposed DRR ASIC is 1.2×1.2 mm2 involving pads.