The Experts below are selected from a list of 54 Experts worldwide ranked by ideXlab platform

Ioannis Papaefstathiou - One of the best experts on this subject based on the ideXlab platform.

  • A Hardware-Engine for Layer-2 classification in low-storage, ultra- high bandwidth environments
    2015
    Co-Authors: Vassilis Papaefstathiou, Ioannis Papaefstathiou
    Abstract:

    Abstract:- Ethernet is the most common Layer-2 network protocol, and it is currently being deployed beyond the tight borders of LANs. In order to accommodate the needs of MANs and WANs, several QoS mechanisms employed at the MAC sublayer of Ethernet have been proposed. These QoS mechanisms require identification of network flows and the classification of Ethernet packets according to certain Ethernet Header fields. In this paper, we propose a classification engine employed at the MAC sublayer which uses an innovative hashing scheme and internal replacement of MAC Vendor IDs; the Hash Based Classification Engine (HBCE) compacts the tables containing the rules associated with certain MAC addresses and supports extremely high speed decisions –at a rate of more than 100Gb/sec-, while its memory needs are significantly lower compared to those of the similar schemes currently used. This engine has been implemented in hardware utilizing less than 0.1mm in a state of the art CMOS technology. As a result HBCE is a very promising candidate for the next-generation Ethernet equipments that need to support classification at Data Link Layer at multi-Gigabit per second network speeds, whereas due to its very low memory requirements and low implementation complexity, it can also be employed very efficiently in lower-bandwidth wireless environments that utilize MAC mechanisms.

  • DATE Designers' Forum - A Hardware-Engine for Layer-2 classification in low-storage, ultra high bandwidth environments
    Proceedings of the Design Automation & Test in Europe Conference, 2006
    Co-Authors: Vassilis Papaefstathiou, Ioannis Papaefstathiou
    Abstract:

    Ethernet is the most common layer-2 network protocol, and it is currently being deployed beyond the tight borders of LANs. In order to accommodate the needs of MANs and WANs, several QoS mechanisms employed at the MAC sublayer of Ethernet have been proposed. These QoS mechanisms require identification of network flows and the classification of Ethernet packets according to certain Ethernet Header fields. In this paper, we propose a classification engine employed at the MAC sublayer which uses an innovative hashing scheme and internal replacement of MAC vendor IDs; the hash based classification engine (HBCE) compacts the tables containing the rules associated with certain MAC addresses and supports extremely high speed decisions - at a rate of more than 100Gb/sec -, while its memory needs are significantly lower compared to those of the similar schemes currently used. This engine has been implemented in hardware utilizing less than 0.1mm2 in a state of the art CMOS technology. As a result HBCE is a very promising candidate for the next-generation Ethernet equipments that need to support classification at data link layer at multi-gigabit per second network speeds, whereas due to its very low memory requirements and low implementation complexity, it can also be employed very efficiently in lower-bandwidth wireless environments that utilize MAC mechanisms

Axel Schneider - One of the best experts on this subject based on the ideXlab platform.

  • DASIP - An in-band reconfigurable network node based on a heterogeneous platform
    2010 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2010
    Co-Authors: Erik Markert, Enrico Billich, C. Tischendorf, U. Pross, T. Leibelt, Ulrich Heinkel, Joachim Knäblein, Axel Schneider
    Abstract:

    This paper describes the implementation of a heterogeneous network node as a reconfigurable application based on embedded ASIC technology. The key points of the paper are the distribution of the reconfiguration data in-band over the network and the in-service-reconfiguration of the network node itself. The node consists of a static ASIC part and three reconfigurable various-grained FPGA-like areas included in one chip. The overall goal is to implement a system that can monitor an Ethernet data stream, extracts configuration data marked by the EtherType field in the Ethernet Header and updates its functionality during operation time.

  • DATE - Demonstration of an in-band reconfiguration data distribution and network node reconfiguration
    2010 Design Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010
    Co-Authors: U. Pross, Erik Markert, Ulrich Heinkel, Joachim Knäblein, Sebastian Goller, Michael Juttner, Jan Langer, Axel Schneider
    Abstract:

    This paper describes the implementation of an FPGA prototype of an application based on embedded ASIC technology. The overall goal is to implement a system that can monitor an Ethernet data stream and extracts configuration data marked by the EtherType field in the Ethernet Header. For evaluation the application is implemented on a prototype consisting of two XILINX FPGA boards. Since the target platform is an ASIC with embedded reconfigurable architectures the prototype is divided in the corresponding parts. One board emulates the embedded reconfigurable architecture that contains the Ethernet MAC. Ethernet packets can reconfigure this MAC. The second board emulates the static part of the application that controls the reconfiguration process.

Vassilis Papaefstathiou - One of the best experts on this subject based on the ideXlab platform.

  • A Hardware-Engine for Layer-2 classification in low-storage, ultra- high bandwidth environments
    2015
    Co-Authors: Vassilis Papaefstathiou, Ioannis Papaefstathiou
    Abstract:

    Abstract:- Ethernet is the most common Layer-2 network protocol, and it is currently being deployed beyond the tight borders of LANs. In order to accommodate the needs of MANs and WANs, several QoS mechanisms employed at the MAC sublayer of Ethernet have been proposed. These QoS mechanisms require identification of network flows and the classification of Ethernet packets according to certain Ethernet Header fields. In this paper, we propose a classification engine employed at the MAC sublayer which uses an innovative hashing scheme and internal replacement of MAC Vendor IDs; the Hash Based Classification Engine (HBCE) compacts the tables containing the rules associated with certain MAC addresses and supports extremely high speed decisions –at a rate of more than 100Gb/sec-, while its memory needs are significantly lower compared to those of the similar schemes currently used. This engine has been implemented in hardware utilizing less than 0.1mm in a state of the art CMOS technology. As a result HBCE is a very promising candidate for the next-generation Ethernet equipments that need to support classification at Data Link Layer at multi-Gigabit per second network speeds, whereas due to its very low memory requirements and low implementation complexity, it can also be employed very efficiently in lower-bandwidth wireless environments that utilize MAC mechanisms.

  • DATE Designers' Forum - A Hardware-Engine for Layer-2 classification in low-storage, ultra high bandwidth environments
    Proceedings of the Design Automation & Test in Europe Conference, 2006
    Co-Authors: Vassilis Papaefstathiou, Ioannis Papaefstathiou
    Abstract:

    Ethernet is the most common layer-2 network protocol, and it is currently being deployed beyond the tight borders of LANs. In order to accommodate the needs of MANs and WANs, several QoS mechanisms employed at the MAC sublayer of Ethernet have been proposed. These QoS mechanisms require identification of network flows and the classification of Ethernet packets according to certain Ethernet Header fields. In this paper, we propose a classification engine employed at the MAC sublayer which uses an innovative hashing scheme and internal replacement of MAC vendor IDs; the hash based classification engine (HBCE) compacts the tables containing the rules associated with certain MAC addresses and supports extremely high speed decisions - at a rate of more than 100Gb/sec -, while its memory needs are significantly lower compared to those of the similar schemes currently used. This engine has been implemented in hardware utilizing less than 0.1mm2 in a state of the art CMOS technology. As a result HBCE is a very promising candidate for the next-generation Ethernet equipments that need to support classification at data link layer at multi-gigabit per second network speeds, whereas due to its very low memory requirements and low implementation complexity, it can also be employed very efficiently in lower-bandwidth wireless environments that utilize MAC mechanisms

Papaefstathiou Ioannis(http://users.isc.tuc.gr/~ipapaefstathiou) - One of the best experts on this subject based on the ideXlab platform.

  • A Hardware-Engine for Layer-2 classification in low-storage, ultra-high bandwidth environments
    Institute of Electrical and Electronics Engineers, 2006
    Co-Authors: Παπαευσταθιου Ιωαννης(http://users.isc.tuc.gr/~ipapaefstathiou), Papaefstathiou Ioannis(http://users.isc.tuc.gr/~ipapaefstathiou)
    Abstract:

    Summarization: Ethernet is the most common layer-2 network protocol, and it is currently being deployed beyond the tight borders of LANs. In order to accommodate the needs of MANs and WANs, several QoS mechanisms employed at the MAC sublayer of Ethernet have been proposed. These QoS mechanisms require identification of network flows and the classification of Ethernet packets according to certain Ethernet Header fields. In this paper, we propose a classification engine employed at the MAC sublayer which uses an innovative hashing scheme and internal replacement of MAC vendor IDs; the hash based classification engine (HBCE) compacts the tables containing the rules associated with certain MAC addresses and supports extremely high speed decisions - at a rate of more than 100Gb/sec -, while its memory needs are significantly lower compared to those of the similar schemes currently used. This engine has been implemented in hardware utilizing less than 0.1mm2 in a state of the art CMOS technology. As a result HBCE is a very promising candidate for the next-generation Ethernet equipments that need to support classification at data link layer at multi-gigabit per second network speeds, whereas due to its very low memory requirements and low implementation complexity, it can also be employed very efficiently in lower-bandwidth wireless environments that utilize MAC mechanismsΠαρουσιάστηκε στο: Proceedings Design, Automation and Test in Europe, 200

Erik Markert - One of the best experts on this subject based on the ideXlab platform.

  • DASIP - An in-band reconfigurable network node based on a heterogeneous platform
    2010 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2010
    Co-Authors: Erik Markert, Enrico Billich, C. Tischendorf, U. Pross, T. Leibelt, Ulrich Heinkel, Joachim Knäblein, Axel Schneider
    Abstract:

    This paper describes the implementation of a heterogeneous network node as a reconfigurable application based on embedded ASIC technology. The key points of the paper are the distribution of the reconfiguration data in-band over the network and the in-service-reconfiguration of the network node itself. The node consists of a static ASIC part and three reconfigurable various-grained FPGA-like areas included in one chip. The overall goal is to implement a system that can monitor an Ethernet data stream, extracts configuration data marked by the EtherType field in the Ethernet Header and updates its functionality during operation time.

  • DATE - Demonstration of an in-band reconfiguration data distribution and network node reconfiguration
    2010 Design Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010
    Co-Authors: U. Pross, Erik Markert, Ulrich Heinkel, Joachim Knäblein, Sebastian Goller, Michael Juttner, Jan Langer, Axel Schneider
    Abstract:

    This paper describes the implementation of an FPGA prototype of an application based on embedded ASIC technology. The overall goal is to implement a system that can monitor an Ethernet data stream and extracts configuration data marked by the EtherType field in the Ethernet Header. For evaluation the application is implemented on a prototype consisting of two XILINX FPGA boards. Since the target platform is an ASIC with embedded reconfigurable architectures the prototype is divided in the corresponding parts. One board emulates the embedded reconfigurable architecture that contains the Ethernet MAC. Ethernet packets can reconfigure this MAC. The second board emulates the static part of the application that controls the reconfiguration process.