The Experts below are selected from a list of 12903 Experts worldwide ranked by ideXlab platform

Y. Zemach - One of the best experts on this subject based on the ideXlab platform.

  • ia 32 Execution Layer a two phase dynamic translator designed to support ia 32 applications on itanium spl reg based systems
    International Symposium on Microarchitecture, 2003
    Co-Authors: L. Baraz, T. Devor, A. Skaletsky, Opher Etzion, Shalom Goldenberg, Yun Wang, Y. Zemach
    Abstract:

    IA-32 Execution Layer (IA-32 EL) is a new technology that executes IA-32 applications on Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium-based platforms is achieved using hardware circuitry on the Itanium processors. This capability will be enhanced with IA-32 EL - software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation. In this paper, we describe aspects of the IA-32 Execution Layer technology, including the general two-phase translation architecture and the usage of a single translator for multiple operating systems. The paper provides details of some of the technical challenges such as precise exception, emulation of FP, MMX, and Intel streaming SIMD extension instructions, and misalignment handling. Finally, the paper presents some performance results.

  • IA-32 Execution Layer: A two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems
    Proceedings of the Annual International Symposium on Microarchitecture MICRO, 2003
    Co-Authors: L. Baraz, T. Devor, A. Skaletsky, Suzanne Goldenberg, Opher Etzion, Yun Wang, Y. Zemach
    Abstract:

    IA-32 Execution Layer (IA-32 EL) is a new technology that executes IA-32 applications on Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium-based platforms is achieved using hardware circuitry on the Itanium processors. This capability will be enhanced with IA-32 EL - software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation. In this paper, we describe aspects of the IA-32 Execution Layer technology, including the general two-phase translation architecture and the usage of a single translator for multiple operating systems. The paper provides details of some of the technical challenges such as precise exception, emulation of FP, MMX, and Intel streaming SIMD extension instructions, and misalignment handling. Finally, the paper presents some performance results.

L. Baraz - One of the best experts on this subject based on the ideXlab platform.

  • ia 32 Execution Layer a two phase dynamic translator designed to support ia 32 applications on itanium spl reg based systems
    International Symposium on Microarchitecture, 2003
    Co-Authors: L. Baraz, T. Devor, A. Skaletsky, Opher Etzion, Shalom Goldenberg, Yun Wang, Y. Zemach
    Abstract:

    IA-32 Execution Layer (IA-32 EL) is a new technology that executes IA-32 applications on Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium-based platforms is achieved using hardware circuitry on the Itanium processors. This capability will be enhanced with IA-32 EL - software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation. In this paper, we describe aspects of the IA-32 Execution Layer technology, including the general two-phase translation architecture and the usage of a single translator for multiple operating systems. The paper provides details of some of the technical challenges such as precise exception, emulation of FP, MMX, and Intel streaming SIMD extension instructions, and misalignment handling. Finally, the paper presents some performance results.

  • IA-32 Execution Layer: A two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems
    Proceedings of the Annual International Symposium on Microarchitecture MICRO, 2003
    Co-Authors: L. Baraz, T. Devor, A. Skaletsky, Suzanne Goldenberg, Opher Etzion, Yun Wang, Y. Zemach
    Abstract:

    IA-32 Execution Layer (IA-32 EL) is a new technology that executes IA-32 applications on Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium-based platforms is achieved using hardware circuitry on the Itanium processors. This capability will be enhanced with IA-32 EL - software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation. In this paper, we describe aspects of the IA-32 Execution Layer technology, including the general two-phase translation architecture and the usage of a single translator for multiple operating systems. The paper provides details of some of the technical challenges such as precise exception, emulation of FP, MMX, and Intel streaming SIMD extension instructions, and misalignment handling. Finally, the paper presents some performance results.

Mykel J Kochenderfer - One of the best experts on this subject based on the ideXlab platform.

  • dynamic real time multimodal routing with hierarchical hybrid planning
    IEEE Intelligent Vehicles Symposium, 2019
    Co-Authors: Shushman Choudhury, Jacob P Knickerbocker, Mykel J Kochenderfer
    Abstract:

    We introduce the problem of Dynamic Real-time Multimodal Routing (DREAMR), which requires planning and executing routes under uncertainty for an autonomous agent. The agent can use multiple modes of transportation in a dynamic transit vehicle network. For instance, a drone can either fly or ride on terrain vehicles for segments of their routes. DREAMR is a difficult problem of sequential decision making under uncertainty with both discrete and continuous variables. We design a novel hierarchical hybrid planning framework to solve the DREAMR problem that exploits its structural decomposability. Our framework consists of a global open-loop planning Layer that invokes and monitors a local closed-loop Execution Layer. Additional abstractions allow efficient and seamless interleaving of planning and Execution. We create a large-scale simulation for DREAMR problems, with each scenario having hundreds of transportation routes and thousands of connection points. Our algorithmic framework significantly outperforms a receding horizon control baseline, in terms of elapsed time to reach the destination and energy expended by the agent.

  • dynamic real time multimodal routing with hierarchical hybrid planning
    arXiv: Artificial Intelligence, 2019
    Co-Authors: Shushman Choudhury, Jacob P Knickerbocker, Mykel J Kochenderfer
    Abstract:

    We introduce the problem of Dynamic Real-time Multimodal Routing (DREAMR), which requires planning and executing routes under uncertainty for an autonomous agent. The agent has access to a time-varying transit vehicle network in which it can use multiple modes of transportation. For instance, a drone can either fly or ride on terrain vehicles for segments of their routes. DREAMR is a difficult problem of sequential decision making under uncertainty with both discrete and continuous variables. We design a novel hierarchical hybrid planning framework to solve the DREAMR problem that exploits its structural decomposability. Our framework consists of a global open-loop planning Layer that invokes and monitors a local closed-loop Execution Layer. Additional abstractions allow efficient and seamless interleaving of planning and Execution. We create a large-scale simulation for DREAMR problems, with each scenario having hundreds of transportation routes and thousands of connection points. Our algorithmic framework significantly outperforms a receding horizon control baseline, in terms of elapsed time to reach the destination and energy expended by the agent.

T. Devor - One of the best experts on this subject based on the ideXlab platform.

  • ia 32 Execution Layer a two phase dynamic translator designed to support ia 32 applications on itanium spl reg based systems
    International Symposium on Microarchitecture, 2003
    Co-Authors: L. Baraz, T. Devor, A. Skaletsky, Opher Etzion, Shalom Goldenberg, Yun Wang, Y. Zemach
    Abstract:

    IA-32 Execution Layer (IA-32 EL) is a new technology that executes IA-32 applications on Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium-based platforms is achieved using hardware circuitry on the Itanium processors. This capability will be enhanced with IA-32 EL - software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation. In this paper, we describe aspects of the IA-32 Execution Layer technology, including the general two-phase translation architecture and the usage of a single translator for multiple operating systems. The paper provides details of some of the technical challenges such as precise exception, emulation of FP, MMX, and Intel streaming SIMD extension instructions, and misalignment handling. Finally, the paper presents some performance results.

  • IA-32 Execution Layer: A two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems
    Proceedings of the Annual International Symposium on Microarchitecture MICRO, 2003
    Co-Authors: L. Baraz, T. Devor, A. Skaletsky, Suzanne Goldenberg, Opher Etzion, Yun Wang, Y. Zemach
    Abstract:

    IA-32 Execution Layer (IA-32 EL) is a new technology that executes IA-32 applications on Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium-based platforms is achieved using hardware circuitry on the Itanium processors. This capability will be enhanced with IA-32 EL - software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation. In this paper, we describe aspects of the IA-32 Execution Layer technology, including the general two-phase translation architecture and the usage of a single translator for multiple operating systems. The paper provides details of some of the technical challenges such as precise exception, emulation of FP, MMX, and Intel streaming SIMD extension instructions, and misalignment handling. Finally, the paper presents some performance results.

A. Skaletsky - One of the best experts on this subject based on the ideXlab platform.

  • ia 32 Execution Layer a two phase dynamic translator designed to support ia 32 applications on itanium spl reg based systems
    International Symposium on Microarchitecture, 2003
    Co-Authors: L. Baraz, T. Devor, A. Skaletsky, Opher Etzion, Shalom Goldenberg, Yun Wang, Y. Zemach
    Abstract:

    IA-32 Execution Layer (IA-32 EL) is a new technology that executes IA-32 applications on Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium-based platforms is achieved using hardware circuitry on the Itanium processors. This capability will be enhanced with IA-32 EL - software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation. In this paper, we describe aspects of the IA-32 Execution Layer technology, including the general two-phase translation architecture and the usage of a single translator for multiple operating systems. The paper provides details of some of the technical challenges such as precise exception, emulation of FP, MMX, and Intel streaming SIMD extension instructions, and misalignment handling. Finally, the paper presents some performance results.

  • IA-32 Execution Layer: A two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems
    Proceedings of the Annual International Symposium on Microarchitecture MICRO, 2003
    Co-Authors: L. Baraz, T. Devor, A. Skaletsky, Suzanne Goldenberg, Opher Etzion, Yun Wang, Y. Zemach
    Abstract:

    IA-32 Execution Layer (IA-32 EL) is a new technology that executes IA-32 applications on Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium-based platforms is achieved using hardware circuitry on the Itanium processors. This capability will be enhanced with IA-32 EL - software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation. In this paper, we describe aspects of the IA-32 Execution Layer technology, including the general two-phase translation architecture and the usage of a single translator for multiple operating systems. The paper provides details of some of the technical challenges such as precise exception, emulation of FP, MMX, and Intel streaming SIMD extension instructions, and misalignment handling. Finally, the paper presents some performance results.