The Experts below are selected from a list of 180 Experts worldwide ranked by ideXlab platform
Minhua Zhou - One of the best experts on this subject based on the ideXlab platform.
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Multi-loop scalable video codec based on high efficiency video coding (HEVC)
2013 IEEE International Conference on Acoustics Speech and Signal Processing, 2013Co-Authors: Do-kyoung Kwon, Madhukar Budagavi, Minhua ZhouAbstract:A multi-loop scalable video coder for high efficiency video coding (HEVC) is proposed in this paper. A coding unit (CU)-level inter-layer sample prediction tool is proposed to Exploit Redundancy between enhancement-layer and up-sampled base-layer pictures. To reduce decoded picture buffer size and memory bandwidth in a multi-loop decoder, a hierarchical inter-layer prediction tool is proposed as well using two picture-level flags. The proposed solution requires minimum amount of changes relative to the single-layer HEVC codec to support HEVC scalable coding, and provides a good complexity and coding efficiency trade-off as revealed by the experimental results.
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ICASSP - Multi-loop scalable video codec based on high efficiency video coding (HEVC)
2013 IEEE International Conference on Acoustics Speech and Signal Processing, 2013Co-Authors: Do-kyoung Kwon, Madhukar Budagavi, Minhua ZhouAbstract:A multi-loop scalable video coder for high efficiency video coding (HEVC) is proposed in this paper. A coding unit (CU)-level inter-layer sample prediction tool is proposed to Exploit Redundancy between enhancement-layer and up-sampled base-layer pictures. To reduce decoded picture buffer size and memory bandwidth in a multi-loop decoder, a hierarchical inter-layer prediction tool is proposed as well using two picture-level flags. The proposed solution requires minimum amount of changes relative to the single-layer HEVC codec to support HEVC scalable coding, and provides a good complexity and coding efficiency trade-off as revealed by the experimental results.
Anantha P Chandrakasan - One of the best experts on this subject based on the ideXlab platform.
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a 249 mpixel s hevc video decoder chip for 4k ultra hd applications
IEEE Journal of Solid-state Circuits, 2014Co-Authors: Mehul Tikekar, Chaotsung Huang, Chiraag Juvekar, Anantha P ChandrakasanAbstract:High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better Exploit Redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm2 in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.
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A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications
IEEE Journal of Solid-State Circuits, 2014Co-Authors: Mehul Tikekar, Chaotsung Huang, Chiraag Juvekar, Anantha P ChandrakasanAbstract:High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better Exploit Redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm2 in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.
Do-kyoung Kwon - One of the best experts on this subject based on the ideXlab platform.
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Multi-loop scalable video codec based on high efficiency video coding (HEVC)
2013 IEEE International Conference on Acoustics Speech and Signal Processing, 2013Co-Authors: Do-kyoung Kwon, Madhukar Budagavi, Minhua ZhouAbstract:A multi-loop scalable video coder for high efficiency video coding (HEVC) is proposed in this paper. A coding unit (CU)-level inter-layer sample prediction tool is proposed to Exploit Redundancy between enhancement-layer and up-sampled base-layer pictures. To reduce decoded picture buffer size and memory bandwidth in a multi-loop decoder, a hierarchical inter-layer prediction tool is proposed as well using two picture-level flags. The proposed solution requires minimum amount of changes relative to the single-layer HEVC codec to support HEVC scalable coding, and provides a good complexity and coding efficiency trade-off as revealed by the experimental results.
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ICASSP - Multi-loop scalable video codec based on high efficiency video coding (HEVC)
2013 IEEE International Conference on Acoustics Speech and Signal Processing, 2013Co-Authors: Do-kyoung Kwon, Madhukar Budagavi, Minhua ZhouAbstract:A multi-loop scalable video coder for high efficiency video coding (HEVC) is proposed in this paper. A coding unit (CU)-level inter-layer sample prediction tool is proposed to Exploit Redundancy between enhancement-layer and up-sampled base-layer pictures. To reduce decoded picture buffer size and memory bandwidth in a multi-loop decoder, a hierarchical inter-layer prediction tool is proposed as well using two picture-level flags. The proposed solution requires minimum amount of changes relative to the single-layer HEVC codec to support HEVC scalable coding, and provides a good complexity and coding efficiency trade-off as revealed by the experimental results.
Mehul Tikekar - One of the best experts on this subject based on the ideXlab platform.
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a 249 mpixel s hevc video decoder chip for 4k ultra hd applications
IEEE Journal of Solid-state Circuits, 2014Co-Authors: Mehul Tikekar, Chaotsung Huang, Chiraag Juvekar, Anantha P ChandrakasanAbstract:High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better Exploit Redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm2 in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.
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A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications
IEEE Journal of Solid-State Circuits, 2014Co-Authors: Mehul Tikekar, Chaotsung Huang, Chiraag Juvekar, Anantha P ChandrakasanAbstract:High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better Exploit Redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm2 in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.
Madhukar Budagavi - One of the best experts on this subject based on the ideXlab platform.
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Multi-loop scalable video codec based on high efficiency video coding (HEVC)
2013 IEEE International Conference on Acoustics Speech and Signal Processing, 2013Co-Authors: Do-kyoung Kwon, Madhukar Budagavi, Minhua ZhouAbstract:A multi-loop scalable video coder for high efficiency video coding (HEVC) is proposed in this paper. A coding unit (CU)-level inter-layer sample prediction tool is proposed to Exploit Redundancy between enhancement-layer and up-sampled base-layer pictures. To reduce decoded picture buffer size and memory bandwidth in a multi-loop decoder, a hierarchical inter-layer prediction tool is proposed as well using two picture-level flags. The proposed solution requires minimum amount of changes relative to the single-layer HEVC codec to support HEVC scalable coding, and provides a good complexity and coding efficiency trade-off as revealed by the experimental results.
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ICASSP - Multi-loop scalable video codec based on high efficiency video coding (HEVC)
2013 IEEE International Conference on Acoustics Speech and Signal Processing, 2013Co-Authors: Do-kyoung Kwon, Madhukar Budagavi, Minhua ZhouAbstract:A multi-loop scalable video coder for high efficiency video coding (HEVC) is proposed in this paper. A coding unit (CU)-level inter-layer sample prediction tool is proposed to Exploit Redundancy between enhancement-layer and up-sampled base-layer pictures. To reduce decoded picture buffer size and memory bandwidth in a multi-loop decoder, a hierarchical inter-layer prediction tool is proposed as well using two picture-level flags. The proposed solution requires minimum amount of changes relative to the single-layer HEVC codec to support HEVC scalable coding, and provides a good complexity and coding efficiency trade-off as revealed by the experimental results.
