The Experts below are selected from a list of 4326 Experts worldwide ranked by ideXlab platform
Jaehyouk Choi - One of the best experts on this subject based on the ideXlab platform.
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an External Capacitor less high psr low dropout regulator using an adaptive supply ripple cancellation technique to the body gate
Asia and South Pacific Design Automation Conference, 2018Co-Authors: Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk ChoiAbstract:This work presents an External-Capacitor-less low-dropout regulator (LDO) that provides high power-supply rejection (PSR) at all low-to-high frequencies. Using the proposed adaptive supply-ripple cancellation (ASRC) technique, where the ripples copied from the supply are injected adaptively to the body-gate, the PSR-hump of conventional LDOs can be suppressed significantly. The proposed LDO was fabricated in a 65-nm CMOS process, and the measured PSRs were less than -36dB at all frequencies from 10kHz to 1GHz, despite changes in a load current (IL) and a dropout voltage (VDO).
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an External Capacitor less ultralow dropout regulator using a loop gain stabilizing technique for high power supply rejection over a wide range of load current
IEEE Transactions on Very Large Scale Integration Systems, 2017Co-Authors: Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seongsik Song, Hongteuk Kim, Ockgoo Lee, Jaehyouk ChoiAbstract:An External Capacitor-less ultra low-dropout (LDO) regulator that can continue to provide high power-supply rejection (PSR) over a wide range of the load current is proposed. Using the loop-gain stabilizer (LGS) to fix the dc level of the output voltage of the error amplifier to the optimal value, the LDO can keep maximizing the unity-gain frequency, while the load current changes widely up to 200 mA. Despite the multiple poles in the regulating loop, the stability can easily be obtained due to an intrinsic left-half plane zero, generated by the auxiliary path of the LGS. The proposed LDO was fabricated in a 40-nm CMOS process, and it had an input voltage of 1.1 V. When the dropout voltage was 0.1 V and the load current was 200 mA, the measured PSRs were −60 and −35 dB at 1 and 10 MHz, respectively. Due to the LGS, the dc loop gain was maintained to be high, resulting in good load and line regulations of $19~\mu {\text{V}}$ /mA and 0.75 mV/V, respectively. While the total current consumption of the LDO was $275~\mu {\text{A}}$ , the LGS consumed only $7~\mu {\text{A}}$ . The area was 0.008 mm2 with 4-pF on-chip capacitance for compensation.
Filippo Spertino - One of the best experts on this subject based on the ideXlab platform.
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Capacitor charging method for i v curve tracer and mppt in photovoltaic systems
Solar Energy, 2015Co-Authors: Filippo Spertino, Jawad Ahmad, Alessandro Ciocia, Paolo Di Leo, Ali Faisal Murtaza, Marcello ChiabergeAbstract:Abstract The Capacitor charging method can be used in Photovoltaic (PV) systems for two typical applications: a very simple and cheap way (1) to trace the I–V curve of a PV generator of whatever size and (2) to track the Maximum Power Point (MPP), especially when the partial shading occurs. The problem is the correct sizing of the Capacitor in order to achieve accurate, uniform and smooth results. In the first application a simplified calculation to design quickly the Capacitor is carried out. This is done only as a function of the main characteristics of the PV array and the most important datasheet parameters of the PV modules. Then, the setup of I–V curve tracers at module, string and array levels is presented: these tracers are useful in the detection of underperformance of PV systems. In the second application a MPPT (MPP Tracker) circuit based on Capacitor charging is designed and simulated in partial shading conditions. In these conditions the Power–Voltage (P–V) curve of a PV array is characterized by the presence of multiple maxima for the bypass diode action. The PV array is isolated from the load for a negligibly short period and is connected to an External Capacitor. During the charging time, the proposed circuit tracks the global MPP. This circuit is easy to implement and shortens the duration needed for scanning the P–V curve of the array.
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pv module parameter characterization from the transient charge of an External Capacitor
IEEE Journal of Photovoltaics, 2013Co-Authors: Filippo Spertino, Jean Sumaili, Horia Andrei, Gianfranco ChiccoAbstract:In the classical model of the photovoltaic (PV) cell/module, based on the single-exponential or double-exponential representation of PV cell/module behavior, parasitic parameters are ignored. Their presence, however, has multiple effects, such as the maximum power point tracking on the current-voltage curve, the switching ON/OFF of the inverters for grid connection, and the electrical safety of persons against indirect contact due to ground leakage currents and lightning phenomena. The effects of parasitic parameters can be visualized in the experimental results gathered through the transient charge of an External Capacitor connected to the PV generator terminals. The impact of the parasitic components is different when considering a single PV module or a PV array composed of several PV modules. At the module scale, an oscillation occurs in the initial part of the current waveform, which indicates the presence of some inductive components. At the array scale, the inductive phenomena are overdamped, and parasitic capacitive effects become predominant. This paper shows how to determine the parameters of an extended model of PV modules embedding the parasitic parameter effects. It starts from the experimental results obtained from the fast-sampled voltage and current waveforms during the transient charge of an External Capacitor. Numerical examples taken from real cases with different PV technologies are provided.
Marcello Chiaberge - One of the best experts on this subject based on the ideXlab platform.
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Capacitor charging method for i v curve tracer and mppt in photovoltaic systems
Solar Energy, 2015Co-Authors: Filippo Spertino, Jawad Ahmad, Alessandro Ciocia, Paolo Di Leo, Ali Faisal Murtaza, Marcello ChiabergeAbstract:Abstract The Capacitor charging method can be used in Photovoltaic (PV) systems for two typical applications: a very simple and cheap way (1) to trace the I–V curve of a PV generator of whatever size and (2) to track the Maximum Power Point (MPP), especially when the partial shading occurs. The problem is the correct sizing of the Capacitor in order to achieve accurate, uniform and smooth results. In the first application a simplified calculation to design quickly the Capacitor is carried out. This is done only as a function of the main characteristics of the PV array and the most important datasheet parameters of the PV modules. Then, the setup of I–V curve tracers at module, string and array levels is presented: these tracers are useful in the detection of underperformance of PV systems. In the second application a MPPT (MPP Tracker) circuit based on Capacitor charging is designed and simulated in partial shading conditions. In these conditions the Power–Voltage (P–V) curve of a PV array is characterized by the presence of multiple maxima for the bypass diode action. The PV array is isolated from the load for a negligibly short period and is connected to an External Capacitor. During the charging time, the proposed circuit tracks the global MPP. This circuit is easy to implement and shortens the duration needed for scanning the P–V curve of the array.
Younghyun Lim - One of the best experts on this subject based on the ideXlab platform.
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an External Capacitor less high psr low dropout regulator using an adaptive supply ripple cancellation technique to the body gate
Asia and South Pacific Design Automation Conference, 2018Co-Authors: Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk ChoiAbstract:This work presents an External-Capacitor-less low-dropout regulator (LDO) that provides high power-supply rejection (PSR) at all low-to-high frequencies. Using the proposed adaptive supply-ripple cancellation (ASRC) technique, where the ripples copied from the supply are injected adaptively to the body-gate, the PSR-hump of conventional LDOs can be suppressed significantly. The proposed LDO was fabricated in a 65-nm CMOS process, and the measured PSRs were less than -36dB at all frequencies from 10kHz to 1GHz, despite changes in a load current (IL) and a dropout voltage (VDO).
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an External Capacitor less ultralow dropout regulator using a loop gain stabilizing technique for high power supply rejection over a wide range of load current
IEEE Transactions on Very Large Scale Integration Systems, 2017Co-Authors: Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seongsik Song, Hongteuk Kim, Ockgoo Lee, Jaehyouk ChoiAbstract:An External Capacitor-less ultra low-dropout (LDO) regulator that can continue to provide high power-supply rejection (PSR) over a wide range of the load current is proposed. Using the loop-gain stabilizer (LGS) to fix the dc level of the output voltage of the error amplifier to the optimal value, the LDO can keep maximizing the unity-gain frequency, while the load current changes widely up to 200 mA. Despite the multiple poles in the regulating loop, the stability can easily be obtained due to an intrinsic left-half plane zero, generated by the auxiliary path of the LGS. The proposed LDO was fabricated in a 40-nm CMOS process, and it had an input voltage of 1.1 V. When the dropout voltage was 0.1 V and the load current was 200 mA, the measured PSRs were −60 and −35 dB at 1 and 10 MHz, respectively. Due to the LGS, the dc loop gain was maintained to be high, resulting in good load and line regulations of $19~\mu {\text{V}}$ /mA and 0.75 mV/V, respectively. While the total current consumption of the LDO was $275~\mu {\text{A}}$ , the LGS consumed only $7~\mu {\text{A}}$ . The area was 0.008 mm2 with 4-pF on-chip capacitance for compensation.
J Silvamartinez - One of the best experts on this subject based on the ideXlab platform.
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an External Capacitor less low drop out regulator with superior psr and fast transient response
International Midwest Symposium on Circuits and Systems, 2013Co-Authors: Saikrishna Ganta, Changjoon Park, Daniel Gitzel, Rafael Rivera, J SilvamartinezAbstract:In this paper, an External Capacitor-less low drop-out (LDO) voltage regulator with superior power supply rejection (PSR) and small transient ripple is described. The proposed LDO has the advantages of wide-band PSR and fast transient response while consuming only 18μA of quiescent current. Simulation results show that the LDO designed in a mainstream 0.18μm CMOS technology presents a PSR better than -55dB up to 1MHz when loaded by a 100pF Capacitor. The peak-to-peak undershoots and overshoots are less than 75mV when load current pulses from 0 to 50mA with 1μs rise/fall times. Load regulation is around 30mV/mA and output voltage deflection is under 75mV when sweeping the load current in the range 0-50mA.
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full on chip cmos low dropout voltage regulator
IEEE Transactions on Circuits and Systems, 2007Co-Authors: R J Milliken, J Silvamartinez, E SanchezsinencioAbstract:This paper proposes a solution to the present bulky External Capacitor low-dropout (LDO) voltage regulators with an External Capacitorless LDO architecture. The large External Capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V Capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed Capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.
