The Experts below are selected from a list of 69 Experts worldwide ranked by ideXlab platform
José L. Sánchez - One of the best experts on this subject based on the ideXlab platform.
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A low-cost strategy to provide full QoS support in Advanced Switching networks
Journal of Systems Architecture, 2007Co-Authors: A. Martinez, Francisco J. Alfaro, R. Martinez, José L. SánchezAbstract:Advanced Switching (AS) is an open-standard Fabric-Interconnect technology that is built over the same physical and link layers as PCI Express technology. Moreover, it includes an optimized transaction layer to enable essential communication capabilities, including protocol encapsulation, peer-to-peer communications, mechanisms to provide quality of service (QoS), enhanced fail-over, high availability, multicast communications, and congestion and system management. In this paper, we propose a strategy to use the AS resources that provides a good performance and QoS support at a low cost. When the system is considered as a whole rather than each element being taken separately, it is possible to use only two virtual channels (VCs) at the switches to provide a service like that with many more VCs. As a result, we obtain a noticeable reduction of silicon area and arbitration time. Our proposal is fully compatible with the AS specification and permits us to provide an adequate performance both for typical multimedia applications and for best-effort traffic.
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ISPA - Studying several proposals for the adaptation of the DTable scheduler to advanced switching
Parallel and Distributed Processing and Applications, 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced Switching (AS) is a new Fabric-Interconnect technology that further enhances the capabilities of PCI Express. On the other hand, the provision of Quality of Service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. A key component for networks with QoS support is the egress link scheduling algorithm. AS defines a table-based scheduler that is simple to implement and can offer good latency bounds with a fixed packet size. However, it does not work properly with variable packet sizes and faces the problem of bounding the bandwidth and latency assignments. In this paper we propose several possible modifications to the original AS table scheduler in order to implement the Deficit Table (DTable) scheduler. This scheduler works properly with variable packet sizes and allows to partially decouple the bandwidth and latency assignments.
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Studying several proposals for the adaptation of the DTable scheduler to advanced switching
Lecture Notes in Computer Science, 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced Switching (AS) is a new Fabric-Interconnect technology that further enhances the capabilities of PCI Express. On the other hand, the provision of Quality of Service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. A key component for networks with QoS support is the egress link scheduling algorithm. AS defines a table-based scheduler that is simple to implement and can offer good latency bounds with a fixed packet size. However, it does not work properly with variable packet sizes and faces the problem of bounding the bandwidth and latency assignments. In this paper we propose several possible modifications to the original AS table scheduler in order to implement the Deficit Table (DTable) scheduler. This scheduler works properly with variable packet sizes and allows to partially decouple the bandwidth and latency assignments.
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ICPADS (1) - Providing quality of service over advanced switching
12th International Conference on Parallel and Distributed Systems - (ICPADS'06), 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced switching (AS) is a new Fabric-Interconnect technology, which provides the advanced features of existing proprietary Fabrics in an open standard. AS is intended to proliferate in multiprocessor, storage, networking, servers, and embedded platform environments. The provision of quality of service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. AS provides some mechanisms, which correctly used permit us to provide QoS. In this paper, we examine these mechanisms and show how to provide QoS based on bandwidth and latency requirements. Furthermore, we propose a new algorithm based on the self-clocked weighted fair queuing (SCFQ) algorithm, which we call SCFQ credit aware (SCFQ-CA), as an implementation of the AS minimum bandwidth egress link scheduler. Finally, we show that the AS table-based scheduler does not work properly with variable packet sizes, and we propose a modification of the table scheduler, based on the deficit table (DTable) scheduler, to solve this drawback.
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Evaluating several implementations for the AS Minimum Bandwidth Egress Link Scheduler
Proceedings of 15th International Conference on Computer Communications and Networks, 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:The relevance of the provision of QoS is taken into account in the definition of the new network technologies like for example advanced switching (AS). AS is a new Fabric- Interconnect technology that further enhances the capabilities of PCI Express, which is the next PCI generation. In this paper we discuss the aspects that must be considered for implementing a specific mechanism for the AS minimum bandwidth egress link scheduler, or just MinBW scheduler. We also propose several implementations for this scheduler, analyze their computational complexity, and compare their performance by simulation. The main differentiating aspect from other Interconnection technologies that must be taken into account when implementing the AS MinBW scheduler is that both the link-level flow control and the scheduling are made at a Virtual Channel (VC) level. This means that the scheduler must have the ability to enable or disable the selection of a given VC based on the flow control information.
R. Martinez - One of the best experts on this subject based on the ideXlab platform.
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Studying several proposals for the adaptation of the DTable scheduler to advanced switching
Lecture Notes in Computer Science, 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced Switching (AS) is a new Fabric-Interconnect technology that further enhances the capabilities of PCI Express. On the other hand, the provision of Quality of Service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. A key component for networks with QoS support is the egress link scheduling algorithm. AS defines a table-based scheduler that is simple to implement and can offer good latency bounds with a fixed packet size. However, it does not work properly with variable packet sizes and faces the problem of bounding the bandwidth and latency assignments. In this paper we propose several possible modifications to the original AS table scheduler in order to implement the Deficit Table (DTable) scheduler. This scheduler works properly with variable packet sizes and allows to partially decouple the bandwidth and latency assignments.
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ISPA - Studying several proposals for the adaptation of the DTable scheduler to advanced switching
Parallel and Distributed Processing and Applications, 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced Switching (AS) is a new Fabric-Interconnect technology that further enhances the capabilities of PCI Express. On the other hand, the provision of Quality of Service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. A key component for networks with QoS support is the egress link scheduling algorithm. AS defines a table-based scheduler that is simple to implement and can offer good latency bounds with a fixed packet size. However, it does not work properly with variable packet sizes and faces the problem of bounding the bandwidth and latency assignments. In this paper we propose several possible modifications to the original AS table scheduler in order to implement the Deficit Table (DTable) scheduler. This scheduler works properly with variable packet sizes and allows to partially decouple the bandwidth and latency assignments.
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ICPADS (1) - Providing quality of service over advanced switching
12th International Conference on Parallel and Distributed Systems - (ICPADS'06), 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced switching (AS) is a new Fabric-Interconnect technology, which provides the advanced features of existing proprietary Fabrics in an open standard. AS is intended to proliferate in multiprocessor, storage, networking, servers, and embedded platform environments. The provision of quality of service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. AS provides some mechanisms, which correctly used permit us to provide QoS. In this paper, we examine these mechanisms and show how to provide QoS based on bandwidth and latency requirements. Furthermore, we propose a new algorithm based on the self-clocked weighted fair queuing (SCFQ) algorithm, which we call SCFQ credit aware (SCFQ-CA), as an implementation of the AS minimum bandwidth egress link scheduler. Finally, we show that the AS table-based scheduler does not work properly with variable packet sizes, and we propose a modification of the table scheduler, based on the deficit table (DTable) scheduler, to solve this drawback.
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NCA - Implementing the Advanced Switching Minimum Bandwidth Egress Link Scheduler
Fifth IEEE International Symposium on Network Computing and Applications (NCA'06), 1Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced Switching (AS) is a new Fabric-Interconnect technology that further enhances the capabilities of PCI Express, which is the next PCI generation. On the other hand, the provision of Quality of Service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. One of the mechanisms that AS provides to support QoS is the minimum bandwidth egress link scheduler, or just MinBW scheduler. In this paper, we propose several implementations of the MinBW scheduler and compare their performance by simulation. These implementations fulfill all the properties that an AS MinBW scheduler must have, including the interaction with the AS link layer flow control.
Francisco J. Alfaro - One of the best experts on this subject based on the ideXlab platform.
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A low-cost strategy to provide full QoS support in Advanced Switching networks
Journal of Systems Architecture, 2007Co-Authors: A. Martinez, Francisco J. Alfaro, R. Martinez, José L. SánchezAbstract:Advanced Switching (AS) is an open-standard Fabric-Interconnect technology that is built over the same physical and link layers as PCI Express technology. Moreover, it includes an optimized transaction layer to enable essential communication capabilities, including protocol encapsulation, peer-to-peer communications, mechanisms to provide quality of service (QoS), enhanced fail-over, high availability, multicast communications, and congestion and system management. In this paper, we propose a strategy to use the AS resources that provides a good performance and QoS support at a low cost. When the system is considered as a whole rather than each element being taken separately, it is possible to use only two virtual channels (VCs) at the switches to provide a service like that with many more VCs. As a result, we obtain a noticeable reduction of silicon area and arbitration time. Our proposal is fully compatible with the AS specification and permits us to provide an adequate performance both for typical multimedia applications and for best-effort traffic.
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ISPA - Studying several proposals for the adaptation of the DTable scheduler to advanced switching
Parallel and Distributed Processing and Applications, 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced Switching (AS) is a new Fabric-Interconnect technology that further enhances the capabilities of PCI Express. On the other hand, the provision of Quality of Service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. A key component for networks with QoS support is the egress link scheduling algorithm. AS defines a table-based scheduler that is simple to implement and can offer good latency bounds with a fixed packet size. However, it does not work properly with variable packet sizes and faces the problem of bounding the bandwidth and latency assignments. In this paper we propose several possible modifications to the original AS table scheduler in order to implement the Deficit Table (DTable) scheduler. This scheduler works properly with variable packet sizes and allows to partially decouple the bandwidth and latency assignments.
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Studying several proposals for the adaptation of the DTable scheduler to advanced switching
Lecture Notes in Computer Science, 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced Switching (AS) is a new Fabric-Interconnect technology that further enhances the capabilities of PCI Express. On the other hand, the provision of Quality of Service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. A key component for networks with QoS support is the egress link scheduling algorithm. AS defines a table-based scheduler that is simple to implement and can offer good latency bounds with a fixed packet size. However, it does not work properly with variable packet sizes and faces the problem of bounding the bandwidth and latency assignments. In this paper we propose several possible modifications to the original AS table scheduler in order to implement the Deficit Table (DTable) scheduler. This scheduler works properly with variable packet sizes and allows to partially decouple the bandwidth and latency assignments.
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ICPADS (1) - Providing quality of service over advanced switching
12th International Conference on Parallel and Distributed Systems - (ICPADS'06), 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:Advanced switching (AS) is a new Fabric-Interconnect technology, which provides the advanced features of existing proprietary Fabrics in an open standard. AS is intended to proliferate in multiprocessor, storage, networking, servers, and embedded platform environments. The provision of quality of service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. AS provides some mechanisms, which correctly used permit us to provide QoS. In this paper, we examine these mechanisms and show how to provide QoS based on bandwidth and latency requirements. Furthermore, we propose a new algorithm based on the self-clocked weighted fair queuing (SCFQ) algorithm, which we call SCFQ credit aware (SCFQ-CA), as an implementation of the AS minimum bandwidth egress link scheduler. Finally, we show that the AS table-based scheduler does not work properly with variable packet sizes, and we propose a modification of the table scheduler, based on the deficit table (DTable) scheduler, to solve this drawback.
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Evaluating several implementations for the AS Minimum Bandwidth Egress Link Scheduler
Proceedings of 15th International Conference on Computer Communications and Networks, 2006Co-Authors: R. Martinez, Francisco J. Alfaro, José L. SánchezAbstract:The relevance of the provision of QoS is taken into account in the definition of the new network technologies like for example advanced switching (AS). AS is a new Fabric- Interconnect technology that further enhances the capabilities of PCI Express, which is the next PCI generation. In this paper we discuss the aspects that must be considered for implementing a specific mechanism for the AS minimum bandwidth egress link scheduler, or just MinBW scheduler. We also propose several implementations for this scheduler, analyze their computational complexity, and compare their performance by simulation. The main differentiating aspect from other Interconnection technologies that must be taken into account when implementing the AS MinBW scheduler is that both the link-level flow control and the scheduling are made at a Virtual Channel (VC) level. This means that the scheduler must have the ability to enable or disable the selection of a given VC based on the flow control information.
Alex K. Jones - One of the best experts on this subject based on the ideXlab platform.
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Interconnect customization for a hardware Fabric
ACM Transactions on Design Automation of Electronic Systems, 2009Co-Authors: Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. JonesAbstract:This article describes several multiplexer-based Interconnection strategies designed to improve energy consumption of stripe-based coarse-grain reconfigurable Fabrics. Application requirements for the architecture as well as two dense subgraphs are extracted from a suite of signal and image processing benchmarks. These statistics are used to drive the strategy of the composition of multiplexer-based Interconnect. The article compares Interconnects that are fully connected between stripes, those with a cardinality of 8:1 to 4:1, and extensions that provide a 5:1 cardinality, limited 6:1 cardinality, and hybrids between 5:1 and 3:1 cardinalities. Additionally, dedicated vertical routes are considered replacing some computational units with dedicated pass-gates. Using a Fabric Interconnect model (FIM) written in XML, we demonstrate that Fabric instances and mappers can be automatically generated using a Web-based design flow. Upon testing these instances, we found that using an 8:1 cardinality Interconnect with 33p of the computational units replaced with dedicated pass-gates provided the best energy versus mappability tradeoff, resulting in a 50p energy improvement over fully connected rows and 20p energy improvement over an 8:1 cardinality Interconnect without dedicated vertical routes.
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Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric 1
Greedy Algorithms, 2008Co-Authors: Colin J. Ihrig, Justin Stander, Mustafa Baz, Brady Hunsaker, Raymond R. Hoare, Oleg A. Prokopyev, Alex K. JonesAbstract:This book chapter describes several greedy heuristics for mapping large data-flow graphs (DFGs) onto a stripe-based coarse-grained reconfigurable Fabric. These DFGs represent the behavior of an application kernel in a high-level synthesis flow to convert computer software into custom computer hardware. The first heuristic is a limited lookahead greedy approach that provides excellent run times and a reasonable quality of result. The second heuristic expands on the first heuristic by introducing a random element into the flow, generating multiple solution instances and selecting the best of the set. Finally, the third heuristic formulates the mapping problem of a limited set of rows using a mixed-integer linear program (MILP) and creates a sliding heuristic to map the entire application. In this chapter we will discuss these heuristics, their run times, and solution quality tradeoffs. The greedy mapping heuristic follows a top-down approach to provide a feasible mapping for any given application kernel. Starting with the top row, it completely places each individual row using a limited look-ahead of two rows. After each row is mapped, the mapper will not modify the mapping of any portion of that row. This mapping approach is deterministic as it uses a priority scheme to determine which elements to place first based on factors such as the number of nodes to which it connects and second based on the desirability of a particular location in the row. While the limited information available to the mapper does not often allow it to produce optimal or minimum-size mappings, its runtime is typically a few seconds or less. We use a Fabric Interconnect model (FIM) file in the mapping flow to define a set of restrictions on what Interconnect lines are available, the capabilities of particular functional units (e.g. dedicated vertical routes versus computational capabilities) in the system, etc. The greedy heuristic is deterministic in the priority system which it uses to place nodes. The second mapping heuristic we explore is based on this greedy algorithm and introduces randomness into the heuristic to make decisions along the priority list. In the first implementation the node selection order is selected randomly. In the second version, weights are assigned to nodes based on the deterministic placement order. Since the heuristic runs so quickly, we can run the heuristic 10’s or possibly 100’s of times and select the best result. This method is also parameterizable with the FIM.
Joshua Randall - One of the best experts on this subject based on the ideXlab platform.
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ISC Workshops - Eliminating Dark Bandwidth: A Data-Centric View of Scalable, Efficient Performance, Post-Moore
Lecture Notes in Computer Science, 2017Co-Authors: Jonathan C. Beard, Joshua RandallAbstract:Most of computing research has focused on the computing technologies themselves versus how full systems make use of them (e.g., memory Fabric, Interconnect, software, and compute elements combined). Technologists have largely failed to look at the compute system as a whole, instead optimizing subsystems mostly in isolation. The result, for example, is that systems are built where applications can only ask for a fixed multiple of data (e.g., 64-bytes from DRAM), even if what is required is far less. This is efficient from a hardware interface perspective, however, it results in consuming valuable bandwidth that is never utilized by the core; this hidden bandwidth is effectively dark to the system. The causes of dark bandwidth are systemic, built into the very core of our virtual memory abstractions and memory interfaces. Continued focus on newer, revolutionary memory technologies to improve surface performance characteristics without a systems focus on reducing data movement will simply push this problem off onto future systems. This paper examines the problem of dark bandwidth and offers a holistic approach to reduce overall data movement within future compute systems.
