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Bedrich J. Hosticka - One of the best experts on this subject based on the ideXlab platform.

  • A CMOS Floating-Point Vector-arithmetic unit
    IEEE Journal of Solid-State Circuits, 1994
    Co-Authors: Dirk Timmermann, H. Hahn, Bedrich J. Hosticka
    Abstract:

    This work describes a Floating-Point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, Vector norm, and phase. The chip has been integrated in 1.6 /spl mu/m double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

H E Shuzhuan - One of the best experts on this subject based on the ideXlab platform.

  • design of Floating Point Vector coprocessor based on fpga
    Computer Engineering, 2012
    Co-Authors: H E Shuzhuan
    Abstract:

    To meet the requirement of a series of complex data processing in modern Digital Signal Processor(DSP),a 64 bit Floating-Point coprocessor specially for Floating-Point complex Vector arithmetic is proposed with the logic resources and IP library of ARM9 and the Field Programmable Gate Array(FPGA) chip from Xilinx.The algorithm of related Floating-Point arithmetic could be revised.Results of the test on the hardware simulation platform show that the Floating-Point complex Vector arithmetic performance is greatly improved by the coprocessor.

Dirk Timmermann - One of the best experts on this subject based on the ideXlab platform.

  • A CMOS Floating-Point Vector-arithmetic unit
    IEEE Journal of Solid-State Circuits, 1994
    Co-Authors: Dirk Timmermann, H. Hahn, Bedrich J. Hosticka
    Abstract:

    This work describes a Floating-Point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, Vector norm, and phase. The chip has been integrated in 1.6 /spl mu/m double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

H. Hahn - One of the best experts on this subject based on the ideXlab platform.

  • A CMOS Floating-Point Vector-arithmetic unit
    IEEE Journal of Solid-State Circuits, 1994
    Co-Authors: Dirk Timmermann, H. Hahn, Bedrich J. Hosticka
    Abstract:

    This work describes a Floating-Point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, Vector norm, and phase. The chip has been integrated in 1.6 /spl mu/m double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

Miriam Leeser - One of the best experts on this subject based on the ideXlab platform.

  • an autonomous Vector scalar Floating Point coprocessor for fpgas
    Field-Programmable Custom Computing Machines, 2011
    Co-Authors: Jainik Kathiara, Miriam Leeser
    Abstract:

    We present a Floating Point Vector Coprocessor that works with the Xilinx embedded processors. The FPVC is completely autonomous from the embedded processor, exploiting parallelism and exhibiting greater speedup than alternative Vector processors. The FPVC supports scalar computation so that loops can be executed independently of the main embedded processor. Floating Point addition, multiplication, division and square root are implemented with the Northeastern University VFLOAT library. The FPVC is parameterized so that the number of Vector lanes and maximum Vector length can be easily modified. We have implemented the FPVC on a Xilinx Virtex 5 connected via the Processor Local Bus (PLB) to the embedded PowerPC. Our results show more than five times improved performance over the PowerPC augmented with the Xilinx Floating Point Unit on applications from linear algebra: QR and Cholesky decomposition.