The Experts below are selected from a list of 315 Experts worldwide ranked by ideXlab platform
Shobha Vasudevan - One of the best experts on this subject based on the ideXlab platform.
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Feature Engineering for Scalable Application-Level Post-Silicon Debugging.
arXiv: Hardware Architecture, 2021Co-Authors: Debjit Pal, Shobha VasudevanAbstract:We present systematic and efficient solutions for both observability enhancement and root-cause diagnosis of post-silicon System-on-Chips (SoCs) validation with diverse usage scenarios. We model Specification of interacting Flows in typical applications for message selection. Our method for message selection optimizes Flow Specification coverage and trace buffer utilization. We define the diagnosis problem as identifying buggy traces as outliers and bug-free traces as inliers/normal behaviors, for which we use unsupervised learning algorithms for outlier detection. Instead of direct application of machine learning algorithms over trace data using the signals as raw features, we use feature engineering to transform raw features into more sophisticated features using domain specific operations. The engineered features are highly relevant to the diagnosis task and are generic to be applied across any hardware designs. We present debugging and root cause analysis of subtle post-silicon bugs in industry-scale OpenSPARC T2 SoC. We achieve a trace buffer utilization of 98.96\% with a Flow Specification coverage of 94.3\% (average). Our diagnosis method was able to diagnose up to 66.7\% more bugs and took up to 847$\times$ less diagnosis time as compared to the manual debugging with a diagnosis precision of 0.769.
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application level hardware tracing for scaling post silicon debug
Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model Specifications of interacting Flows in typical applications. Our method optimizes trace buffer utilization and Flow Specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace buffer utilization of 98.96% with a Flow Specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
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DAC - Application level hardware tracing for scaling post-silicon debug
Proceedings of the 55th Annual Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model Specifications of interacting Flows in typical applications. Our method optimizes trace buffer utilization and Flow Specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace buffer utilization of 98.96% with a Flow Specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
Debjit Pal - One of the best experts on this subject based on the ideXlab platform.
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Feature Engineering for Scalable Application-Level Post-Silicon Debugging.
arXiv: Hardware Architecture, 2021Co-Authors: Debjit Pal, Shobha VasudevanAbstract:We present systematic and efficient solutions for both observability enhancement and root-cause diagnosis of post-silicon System-on-Chips (SoCs) validation with diverse usage scenarios. We model Specification of interacting Flows in typical applications for message selection. Our method for message selection optimizes Flow Specification coverage and trace buffer utilization. We define the diagnosis problem as identifying buggy traces as outliers and bug-free traces as inliers/normal behaviors, for which we use unsupervised learning algorithms for outlier detection. Instead of direct application of machine learning algorithms over trace data using the signals as raw features, we use feature engineering to transform raw features into more sophisticated features using domain specific operations. The engineered features are highly relevant to the diagnosis task and are generic to be applied across any hardware designs. We present debugging and root cause analysis of subtle post-silicon bugs in industry-scale OpenSPARC T2 SoC. We achieve a trace buffer utilization of 98.96\% with a Flow Specification coverage of 94.3\% (average). Our diagnosis method was able to diagnose up to 66.7\% more bugs and took up to 847$\times$ less diagnosis time as compared to the manual debugging with a diagnosis precision of 0.769.
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application level hardware tracing for scaling post silicon debug
Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model Specifications of interacting Flows in typical applications. Our method optimizes trace buffer utilization and Flow Specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace buffer utilization of 98.96% with a Flow Specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
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DAC - Application level hardware tracing for scaling post-silicon debug
Proceedings of the 55th Annual Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model Specifications of interacting Flows in typical applications. Our method optimizes trace buffer utilization and Flow Specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace buffer utilization of 98.96% with a Flow Specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
Thierry Gautier - One of the best experts on this subject based on the ideXlab platform.
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translation validation for synchronous data Flow Specification in the signal compiler
Formal Techniques for (Networked and) Distributed Systems, 2015Co-Authors: Van Chan Ngo, Jeanpierre Talpin, Thierry GautierAbstract:We present a method to construct a validator based on translation validation approach to prove the value-equivalence of variables in the compilation of the Signal compiler. The computation of output signals in a Signal program and their counterparts in the generated C code is represented by a Synchronous Data-Flow Value-Graph (Sdvg). Our validator proves that every output signal and its counterpart variable have the same values by transforming the Sdvg graph.
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FORTE - Translation Validation for Synchronous Data-Flow Specification in the SIGNAL Compiler
Formal Techniques for Distributed Objects Components and Systems, 2015Co-Authors: Van Chan Ngo, Jeanpierre Talpin, Thierry GautierAbstract:We present a method to construct a validator based on translation validation approach to prove the value-equivalence of variables in the compilation of the Signal compiler. The computation of output signals in a Signal program and their counterparts in the generated C code is represented by a Synchronous Data-Flow Value-Graph (Sdvg). Our validator proves that every output signal and its counterpart variable have the same values by transforming the Sdvg graph.
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Towards SMV model checking of signal (multi-clocked) Specifications
2009Co-Authors: Julio C. Peralta, Thierry GautierAbstract:Signal is a high-level data-Flow Specification language that equally allows multi-clocked descriptions as well as single-clocked ones. It has a formal semantics and is supported by several formal tools for simulation and static validation. This generality renders it useful for various Specification, simulation, and verification tasks in embedded system design. SMV, in turn, is a language and model checker where synchronous models are single-clocked by definition. Roughly, we use standard techniques to describe clocks by Boolean variables, with the advantage that the number of such variables is kept to a minimum through a static analysis provided by the Signal compiler. In particular, we propose a translation from possibly multi-clocked Signal Specifications into SMV Specifications for their corresponding verification by model checking.
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Polychronous Design of Real-Time Applications with Signal
2008Co-Authors: Thierry Gautier, Paul Le Guernic, Jeanpierre TalpinAbstract:This paper provides an introduction to the synchronous, multi-clocked, data-Flow Specification language Signal. The main operators are described and their use is illustrated through a few simple examples. Basic techniques for compiling Signal programs are outlined.
Sandip Ray - One of the best experts on this subject based on the ideXlab platform.
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application level hardware tracing for scaling post silicon debug
Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model Specifications of interacting Flows in typical applications. Our method optimizes trace buffer utilization and Flow Specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace buffer utilization of 98.96% with a Flow Specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
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DAC - Application level hardware tracing for scaling post-silicon debug
Proceedings of the 55th Annual Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model Specifications of interacting Flows in typical applications. Our method optimizes trace buffer utilization and Flow Specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace buffer utilization of 98.96% with a Flow Specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
Abhishek Sharma - One of the best experts on this subject based on the ideXlab platform.
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application level hardware tracing for scaling post silicon debug
Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model Specifications of interacting Flows in typical applications. Our method optimizes trace buffer utilization and Flow Specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace buffer utilization of 98.96% with a Flow Specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
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DAC - Application level hardware tracing for scaling post-silicon debug
Proceedings of the 55th Annual Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model Specifications of interacting Flows in typical applications. Our method optimizes trace buffer utilization and Flow Specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace buffer utilization of 98.96% with a Flow Specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.