The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Satoshi Nagata - One of the best experts on this subject based on the ideXlab platform.
-
physical cell id detection probability using synchronization signals of nb iot radio interface in 28 ghz band
Vehicular Technology Conference, 2020Co-Authors: Daisuke Inoue, Kyogo Ota, Satoshi NagataAbstract:This paper presents the physical-layer cell identity (PCID) detection probability using the narrowband primary synchronization signal (NPSS) and narrowband secondary synchronization signal (NSSS) based on the narrowband Internet-of-Things (NB-IoT) radio interface considering Frequency offset and the maximum Doppler Frequency in the 28-GHz band. Simulation results show that autocorrelation based NPSS detection achieves almost the same PCID detection probability as that for cross-correlation based NPSS detection using Frequency offset estimation and compensation before the NPSS received timing detection, while the former achieves a lower level of computational complexity than the latter. We also show that when using autocorrelation based NPSS detection, the loss in the PCID detection probability at the carrier Frequency of $f_{c}=28$ GHz compared to that for $f_{c}=3.5$ GHz is only approximately 5% at the average received SNR of 0dB when the Frequency Error of a temperature compensated crystal oscillator of a set of user equipment (UE) is 20 ppm. Therefore, we conclude that the multiplexing schemes and sequences of NPSS and NSSS based on the NB-IoT radio interface associated with autocorrelation based NPSS detection will be applicable to the 28-GHz Frequency spectra.
-
physical cell id detection probability using synchronization signals for nr radio interface in 28 ghz band
Asia-Pacific Conference on Communications, 2019Co-Authors: Kyogo Ota, Satoshi NagataAbstract:This paper presents the physical-layer cell identity (PCID) detection probability using the primary synchronization signal (PSS) and secondary synchronization signal (SSS) for the New Radio (NR) radio interface considering the large Frequency offset in the 28-GHz band. Simulation results show that crosscorrelation based PSS detection achieves a slightly higher PCID detection probability compared to autocorrelation based PSS detection in the lower average received signal-to-noise power ratio (SNR) below approximately 0 dB for the subcarrier spacings (SCSs) of 120 and 240 kHz. Meanwhile, the required computational complexity for the PCID detection of the latter method is much lower than the former method. We also show that when the Frequency Error of a standard oscillator of a set of user equipment is e = 20 ppm, the PCID detection probability is decreased by only approximately 28 (22)% and 3 (6)% compared to that without Frequency offset at the average received SNR of −10 and 0 dB, respectively, for the SCS of 240 (120) kHz. We conclude that the multiplexing scheme for the PSS and SSS and their sequences are effective in achieving a high PCID detection probability considering the large Frequency offset even with e = 30 ppm in the 28-GHz band.
-
Performance of Physical Cell ID Detection Probability Considering Frequency Offset for NR Radio Interface
2019 IEEE 90th Vehicular Technology Conference (VTC2019-Fall), 2019Co-Authors: Kyogo Ota, Aya Shimura, Satoshi NagataAbstract:This paper presents the physical-layer cell identity (PCID) detection probability considering Frequency offset for 5th generation (5G) new radio (NR). We compare the primary synchronization signal (PSS) and PCID detection probabilities of three PSS detection methods: cross-correlation based detection before Frequency offset (FO) estimation and compensation, that after FO estimation and compensation, and autocorrelation based detection at a set of user equipment. Link- level simulation results show that the cross- correlation based PSS detection before the FO estimation and compensation achieves the highest PSS and PCID detection probabilities in the carrier Frequency fc region lower than approximately 14 GHz at the average received signal-to-noise power ratio of 0 dB for the standard oscillator Frequency Error of 1 ppm. The cross-correlation based PSS detection after the FO estimation and compensation achieves much higher PSS and PCID detection probabilities than that before the FO estimation and compensation for the fc region higher than approximately 14 GHz. The PCID detection probability of the cross-correlation based PSS detection after the FO estimation and compensation is close to that of the autocorrelation based PSS detection according to the increase in the fc value. Therefore, we conclude that by switching the cross- correlation based PSS detection methods before and after the FO estimation and compensation, the PSS and secondary synchronization signal structures based on the NR radio interface achieve a high PCID detection probability for the fc value up to 60 GHz.
-
initial cell search method based on two step Frequency offset estimation for small cells in heterogeneous networks
Vehicular Technology Conference, 2016Co-Authors: Naoki Noguchi, Satoshi Nagata, Mamoru Sawahashi, Yoshihisa KishiyamaAbstract:This paper proposes a fast initial cell search method based on two-step Frequency offset estimation for a small cell in Long Term Evolution (LTE) heterogeneous networks using different Frequency spectra. In the proposed cell search method, a set of user equipment (UE) first estimates the Frequency offset of a received primary synchronization signal (PSS) from a macrocell and computes the Frequency offset of a received PSS for a small cell in Step 1 assuming the same Frequency Error of a temperature compensated crystal oscillator (TCXO) of a UE. The UE detects the PSS received timing from the maximum PSS correlation after compensating for the Frequency offset by using the estimated value in Step 1 for the small cell. In Step 2, the UE estimates the residual Frequency offset by taking a partial correlation of the PSS from the small cell. The UE detects the best secondary synchronization signal (SSS) sequence by taking the SSS sequence correlation for the received signal after compensating for the Frequency offset using the estimated value in Step 2. System- level simulation results show that the proposed cell search method achieves a fast initial cell search time within approximately 150 ms to satisfy the cell ID detection probability of 95% even for the carrier Frequency of a small cell up to 6 and 11 GHz, assuming the free-running Frequency Error of the UE TCXO of 3 and 1 ppm, respectively.
Kangyoon Lee - One of the best experts on this subject based on the ideXlab platform.
-
an ultra low power super regeneration oscillator based transceiver with 177 mu w leakage compensated pll and automatic quench waveform generator
IEEE Transactions on Microwave Theory and Techniques, 2013Co-Authors: Hyunggu Park, J Y Lee, Jeonga Jang, Jaehyeong Jang, Dongsoo Lee, Hongjin Kim, Seong Joong Kim, Sanggug Lee, Kangyoon LeeAbstract:An ultra-low-power super regeneration oscillator (SRO) transceiver with a 177- μW ultra-low-power phase-locked loop (PLL) and automatic quench waveform generator (QWG) is presented. In order to decrease the PLL power consumption, the leakage current is measured at the VCO control voltage node, and the control voltage is compensated by the digital part. As a result, the Frequency can be maintained near 2.37 GHz after the PLL is turned off. An automatic QWG circuit that can search for the critical current of the SRO automatically is proposed in order to mitigate the process, voltage, temperature variations of the conventional QWG. This chip is implemented using 90-nm CMOS technology. The die area of the full transceiver is 3 mm × 4 mm and that of the PLL is 0.4 mm × 0.9 mm. The leakage compensation and high-Q voltage-controlled oscillator (VCO) approach results in a Frequency offset of 70 kHz and fluctuation of ±75 kHz (the maximum Frequency Error is 145 kHz at 60 ppm). The phase noise of the VCO output at 2.37 GHz is -103.5 dBc/Hz at 1-MHz offset. The average power consumption of the PLL is 177 μW from a 1.2-V supply voltage.
Pavan Kumar Hanumolu - One of the best experts on this subject based on the ideXlab platform.
-
a 4 to 10 5 gb s continuous rate digital clock and data recovery with automatic Frequency acquisition
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Wooseok Choi, Tejasvi Anand, Amr Elshazly, Ahmed Elkholy, Mrunmay Talegaonkar, Saurabh Saxena, Pavan Kumar HanumoluAbstract:A continuous-rate digital clock and data recovery (CDR) with automatic Frequency acquisition is presented. The proposed automatic Frequency acquisition scheme implemented using a conventional bang–bang phase detector (BBPD) requires minimum additional hardware, is immune to input data transition density, and is applicable to subrate CDRs. A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide Frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs. The CDR is implemented using a digital D/PLL architecture to decouple JTRAN bandwidth from jitter tolerance (JTOL) corner Frequency, eliminate jitter peaking, and remove JTRAN dependence on BBPD gain. Fabricated in a 65 nm CMOS process, the prototype CDR achieves Error-free operation (BER ${\rm{ ) from 4 to 10.5 Gb/s with pseudorandom binary sequence (PRBS) data sequences ranging from PRBS7 to PRBS31. The proposed automatic Frequency acquisition scheme always locks the CDR loop within 1000 ppm residual Frequency Error in worst case. At 10 Gb/s, the CDR consumes 22.5 ${\rm{\,mW}}$ power and achieves a recovered clock long-term jitter of 2.2 ${\rm ps_{rms}}$ /24.0 ${\rm{ ps_{pp}}}$ with PRBS31 input data. The measured JTRAN bandwidth and JTOL corner frequencies are 0.2 and 9 MHz, respectively.
-
design and analysis of low power high Frequency robust sub harmonic injection locked clock multipliers
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Ahmed Elkholy, Tejasvi Anand, Mrunmay Talegaonkar, Pavan Kumar HanumoluAbstract:A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital Frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the proposed FTL continuously tunes the oscillator’s free-running Frequency to ensure robust operation across PVT variations. The FTL resolves the race condition existing in injection-locked PLLs by decoupling Frequency tuning from the injection path, such that the phase-locking condition is only determined by the injection path. This paper also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection-locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO’s lock-in range, and the impact of Frequency Error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of $0.25\;\text{mm}^2$ . The prototype ILCM generates output clock in the range of 6.75–8.25 GHz by multiplying the reference clock by 64. It achieves superior integrated jitter performance of $190\;\text{fs}_{\text{rms}}$ , while consuming 2.25 mW power. This translates to an excellent figure-of-merit (FoM) of $-251\;\text{dB}$ , which is the best reported high-Frequency clock multiplier.
-
a burst mode digital receiver with programmable input jitter filtering for energy proportional links
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Wooseok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar HanumoluAbstract:A full-rate burst-mode receiver that achieves fast on/off operation needed for energy-proportional links is presented. By injecting input data edges into the oscillator embedded in a classical Type-II digital clock and data recovery (CDR) circuit, the proposed receiver achieves instantaneous phase-locking and input jitter filtering simultaneously. In other words, the proposed CDR combines the advantages of conventional feed-forward and feedback architectures to achieve energy-proportional operation. By controlling the number of data edges injected into the oscillator, both the jitter transfer bandwidth and the jitter tolerance corner are accurately controlled. The feedback loop also corrects for any Frequency Error and helps improve CDR's immunity to oscillator Frequency drift during the power-on and -off states. This also improves CDR's tolerance to consecutive identical digits present in the input data. Fabricated in a 90 nm CMOS process, the prototype receiver instantaneously locks onto the very first data edge and consumes 6.1 mW at 2.2 Gb/s. Owing to its short power-on time, the receiver's energy efficiency varies only from 2.77 pJ/bit to 3.87 pJ/bit when the effective data rate is varied from 0.44 Gb/s to 2.2 Gb/s. Input sensitivity of the receiver is 36 mV for a BER of 10 -12 .
Giorgio Santarelli - One of the best experts on this subject based on the ideXlab platform.
-
an agile laser with ultra low Frequency noise and high sweep linearity
Optics Express, 2010Co-Authors: Haifeng Jiang, A Clairon, Fabien Kefelian, P Lemonde, Giorgio SantarelliAbstract:We report on a fiber-stabilized agile laser with ultra-low Frequency noise. The Frequency noise power spectral density is comparable to that of an ultra-stable cavity stabilized laser at Fourier frequencies higher than 30 Hz. When it is chirped at a constant rate of ~ 40 MHz/s, the max non-linearity Frequency Error is about 50 Hz peak-to-peak over more than 600 MHz tuning range. The Rayleigh backscattering is found to be a significant Frequency noise source dependent on fiber length, chirping rate and the power imbalance of the interferometer arms. We analyze this effect both theoretically and experimentally and put forward techniques to reduce this noise contribution.
Dimitrios Peroulis - One of the best experts on this subject based on the ideXlab platform.
-
high q tunable evanescent mode cavity siw resonators and filters with contactless tuners
IEEE Transactions on Microwave Theory and Techniques, 2019Co-Authors: Mahmoud Abdelfattah, Dimitrios PeroulisAbstract:This paper presents a novel method to widely tune high-quality factor evanescent-mode cavity resonators and filters using contactless tuners. The proposed method resolves multiple challenges facing reliable manufacturing and operation of these filters by avoiding the attachment of the flexible tuner to the cavity and replacing it with capacitive contactless tuners. This paper discusses the design consideration and tradeoffs as well as demonstrates the performance of the proposed concept using the substrate-integrated-waveguide technology. The resonators demonstrate more than octave tuning range (TR), quality factor up to 650, and power handling exceeding 100 W. In addition, the second-order bandpass filters are demonstrated, along with the long-term measurements, showing better than 1.17% Frequency Error after a 15-h stability test, and less than 1.47% Frequency Error after a 450 cycles repeatability test over an octave TR from 1.8 to 3.6 GHz.