The Experts below are selected from a list of 309 Experts worldwide ranked by ideXlab platform
Kari Halonen - One of the best experts on this subject based on the ideXlab platform.
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Digital Modulator with Bandpass Delta-Sigma Modulator
Analog Integrated Circuits and Signal Processing, 2005Co-Authors: Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari HalonenAbstract:A digital quadrature modulator with a bandpass ΔΣ-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f _ s /4, − f _ s /4 ( f _ s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass ΔΣ modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm^2 (0.13 μm CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter Full-Scale Output current 11.5 mA).
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A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS Output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current: 11.5 mA).
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CICC - A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the direct digital synthesizer (DDS) Output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current 11.5 mA).
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A digital modulator with bandpass delta-sigma modulator
Proceedings of the 30th European Solid-State Circuits Conference, 2004Co-Authors: Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari HalonenAbstract:A digital quadrature modulator with a bandpass /spl Delta//spl Sigma/-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4, (f/sub s/ is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass /spl Delta//spl Sigma/ modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz. (D/A converter Full-Scale Output current 11.5 mA).
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A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the direct digital synthesizer (DDS) Output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current 11.5 mA).
Jonne Lindeberg - One of the best experts on this subject based on the ideXlab platform.
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Digital Modulator with Bandpass Delta-Sigma Modulator
Analog Integrated Circuits and Signal Processing, 2005Co-Authors: Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari HalonenAbstract:A digital quadrature modulator with a bandpass ΔΣ-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f _ s /4, − f _ s /4 ( f _ s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass ΔΣ modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm^2 (0.13 μm CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter Full-Scale Output current 11.5 mA).
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A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS Output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current: 11.5 mA).
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CICC - A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the direct digital synthesizer (DDS) Output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current 11.5 mA).
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A digital modulator with bandpass delta-sigma modulator
Proceedings of the 30th European Solid-State Circuits Conference, 2004Co-Authors: Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari HalonenAbstract:A digital quadrature modulator with a bandpass /spl Delta//spl Sigma/-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4, (f/sub s/ is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass /spl Delta//spl Sigma/ modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz. (D/A converter Full-Scale Output current 11.5 mA).
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A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the direct digital synthesizer (DDS) Output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current 11.5 mA).
Johan Sommarek - One of the best experts on this subject based on the ideXlab platform.
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Digital Modulator with Bandpass Delta-Sigma Modulator
Analog Integrated Circuits and Signal Processing, 2005Co-Authors: Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari HalonenAbstract:A digital quadrature modulator with a bandpass ΔΣ-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f _ s /4, − f _ s /4 ( f _ s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass ΔΣ modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm^2 (0.13 μm CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter Full-Scale Output current 11.5 mA).
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A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS Output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current: 11.5 mA).
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CICC - A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the direct digital synthesizer (DDS) Output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current 11.5 mA).
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A digital modulator with bandpass delta-sigma modulator
Proceedings of the 30th European Solid-State Circuits Conference, 2004Co-Authors: Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari HalonenAbstract:A digital quadrature modulator with a bandpass /spl Delta//spl Sigma/-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4, (f/sub s/ is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass /spl Delta//spl Sigma/ modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz. (D/A converter Full-Scale Output current 11.5 mA).
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A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the direct digital synthesizer (DDS) Output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current 11.5 mA).
Jouko Vankka - One of the best experts on this subject based on the ideXlab platform.
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Digital Modulator with Bandpass Delta-Sigma Modulator
Analog Integrated Circuits and Signal Processing, 2005Co-Authors: Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari HalonenAbstract:A digital quadrature modulator with a bandpass ΔΣ-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f _ s /4, − f _ s /4 ( f _ s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass ΔΣ modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm^2 (0.13 μm CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter Full-Scale Output current 11.5 mA).
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A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS Output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current: 11.5 mA).
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CICC - A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the direct digital synthesizer (DDS) Output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current 11.5 mA).
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A digital modulator with bandpass delta-sigma modulator
Proceedings of the 30th European Solid-State Circuits Conference, 2004Co-Authors: Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari HalonenAbstract:A digital quadrature modulator with a bandpass /spl Delta//spl Sigma/-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4, (f/sub s/ is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass /spl Delta//spl Sigma/ modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz. (D/A converter Full-Scale Output current 11.5 mA).
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A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari HalonenAbstract:In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the direct digital synthesizer (DDS) Output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with Output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter Full-Scale Output current 11.5 mA).
A. Sangiovanni-vincentelli - One of the best experts on this subject based on the ideXlab platform.
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A module generator for high-speed CMOS current Output digital/analog converters
IEEE Journal of Solid-State Circuits, 1996Co-Authors: R.r. Neff, P.r. Gray, A. Sangiovanni-vincentelliAbstract:A module generator (DSYN) creates optimized digital/analog converter (DAC) layouts given a set of specifications including performance constraints, a description of the implementation technology, and a set of design parameters. The generation process consists of a synthesis step followed by a layout step. During synthesis, a new constrained optimization method is coupled with combination of circuit simulation and DAC design equations. The layout step uses stretching and tiling operations on a set of primitive cells. Prototypes have been demonstrated for an 8-b, 100-MS/s specification, driving a 37.5-ohm video load, and a static 10-b specification, driving a 4 mA Full-Scale Output current. Both designs use a 5-V supply in a 1.2 /spl mu/m CMOS process.
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A module generator for high speed CMOS current Output digital/analog converters
Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995Co-Authors: R.r. Neff, P.r. Gray, A. Sangiovanni-vincentelliAbstract:This paper presents a module generator for Digital/Analog Converter (DAC) circuits. A combination of circuit simulation and DAC design equations is used to estimate performance. A new constrained optimization method is used to determine design variable values. The layout is created using stretching and tiling operations on a set of primitive cells. Close coupling of optimization and layout allows accurate incorporation of layout parasitics in optimization. Prototypes have been demonstrated for an 8-bit, 100-MHz specification, driving a 37.5-ohm video load, and a static 10-bit specification, driving a 4 mA Full-Scale Output current. Both designs use a 5-V supply in a standard 1.2 /spl mu/m CMOS process.
