Fundamental Block

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Ali Ajami - One of the best experts on this subject based on the ideXlab platform.

  • symmetric and asymmetric design and implementation of new cascaded multilevel inverter topology
    IEEE Transactions on Power Electronics, 2014
    Co-Authors: Ataollah Mokhberdoran, Ali Ajami
    Abstract:

    Nowadays, use of multilevel inverters in high-power applications clearly can be seen. High quality and lower distortion of the output voltage and low Blocking voltage of semiconductor switches are being presented as the major privileges of the multilevel inverter compared to the traditional voltage source inverter. In this paper, a new topology of multilevel inverter is proposed as Fundamental Block. The proposed topology is generalized using series connection of the Fundamental Blocks. The proposed multilevel inverter has been analyzed in both symmetric and asymmetric operation modes. A great perfection in voltage levels number with minimum switching devices has been obtained in both symmetric and asymmetric modes. Thereafter, a detailed study of losses and peak inverse voltage (PIV) of the proposed multilevel inverter is given. Also, in continuation, a comparison between the proposed topology and the traditional one and a recently developed topology is carried out. Finally, a computer simulation using MATLAB/Simulink is presented and a laboratory prototype implementation verifies the results.

Ataollah Mokhberdoran - One of the best experts on this subject based on the ideXlab platform.

  • symmetric and asymmetric design and implementation of new cascaded multilevel inverter topology
    IEEE Transactions on Power Electronics, 2014
    Co-Authors: Ataollah Mokhberdoran, Ali Ajami
    Abstract:

    Nowadays, use of multilevel inverters in high-power applications clearly can be seen. High quality and lower distortion of the output voltage and low Blocking voltage of semiconductor switches are being presented as the major privileges of the multilevel inverter compared to the traditional voltage source inverter. In this paper, a new topology of multilevel inverter is proposed as Fundamental Block. The proposed topology is generalized using series connection of the Fundamental Blocks. The proposed multilevel inverter has been analyzed in both symmetric and asymmetric operation modes. A great perfection in voltage levels number with minimum switching devices has been obtained in both symmetric and asymmetric modes. Thereafter, a detailed study of losses and peak inverse voltage (PIV) of the proposed multilevel inverter is given. Also, in continuation, a comparison between the proposed topology and the traditional one and a recently developed topology is carried out. Finally, a computer simulation using MATLAB/Simulink is presented and a laboratory prototype implementation verifies the results.

Dohy Hong - One of the best experts on this subject based on the ideXlab platform.

  • Understanding differential equations through diffusion point of view: non-symmetric discrete equations
    arXiv: Numerical Analysis, 2012
    Co-Authors: Dohy Hong
    Abstract:

    In this paper, we propose a new adaptation of the D-iteration algorithm to numerically solve the differential equations. This problem can be reinterpreted in 2D or 3D (or higher dimensions) as a limit of a diffusion process where the boundary or initial conditions are replaced by fluid catalysts. It has been shown that pre-computing the diffusion process for an elementary catalyst case as a Fundamental Block of a class of differential equations, the computation efficiency can be greatly improved. Here, we explain how the diffusion point of view can be applied to decompose the fluid diffusion process per direction and how to handle non-symmetric discrete equations. The method can be applied on the class of problems that can be addressed by the Gauss-Seidel iteration, based on the linear approximation of the differential equations.

  • Understanding differential equations through diffusion point of view
    arXiv: Numerical Analysis, 2012
    Co-Authors: Dohy Hong
    Abstract:

    In this paper, we propose a new adaptation of the D-iteration algorithm to numerically solve the differential equations. This problem can be reinterpreted in 2D or 3D (or higher dimensions) as a limit of a diffusion process where the boundary or initial conditions are replaced by fluid catalysts. Pre-computing the diffusion process for an elementary catalyst case as a Fundamental Block of a class of differential equations, we show that the computation efficiency can be greatly improved. The method can be applied on the class of problems that can be addressed by the Gauss-Seidel iteration, based on the linear approximation of the differential equations.

Darshana N. Sankhe - One of the best experts on this subject based on the ideXlab platform.

  • Implementation of Harmonic Oscillator Using Xilinx System Generator
    Intelligent Systems Design and Applications, 2020
    Co-Authors: Darshana N. Sankhe, Rajendra R. Sawant, Y. Srinivas Rao
    Abstract:

    Advances in technology demands replacement of all analog Blocks by its counter digital Blocks. Harmonic oscillator (HO) is a mathematical implementation, facilitates generation of sinusoidal waveform, with adjustable frequency, amplitude and harmonics of Fundamental frequency with different phase shifts. It is a Fundamental Block for many communication systems and power control applications.This paper presents implementation of harmonic oscillator using different discretization techniques to test its stability. Most stable hybrid method is then used for generation of pulse width modulation (PWM) pulses, used in power control applications. Further using HO, an Amplitude Shift Keying (ASK) modulation system is implemented to witness its communication applications. HO simulation model is developed using Xilinx System Generator (XSG) in Matlab Simulink. Its VHDL simulation and synthesis is done to verify the functionality and identify the implementation resources required by various discretization methods. Hardware implementation is tested on Spartun-7 Field Programmable Gate Array (FPGA) platform.

  • ISDA (2) - Implementation of Harmonic Oscillator Using Xilinx System Generator
    Advances in Intelligent Systems and Computing, 2019
    Co-Authors: Darshana N. Sankhe, Rajendra Sawant, Y. Srinivas Rao
    Abstract:

    Advances in technology demands replacement of all analog Blocks by its counter digital Blocks. Harmonic oscillator (HO) is a mathematical implementation, facilitates generation of sinusoidal waveform, with adjustable frequency, amplitude and harmonics of Fundamental frequency with different phase shifts. It is a Fundamental Block for many communication systems and power control applications.

Y. Srinivas Rao - One of the best experts on this subject based on the ideXlab platform.

  • Implementation of Harmonic Oscillator Using Xilinx System Generator
    Intelligent Systems Design and Applications, 2020
    Co-Authors: Darshana N. Sankhe, Rajendra R. Sawant, Y. Srinivas Rao
    Abstract:

    Advances in technology demands replacement of all analog Blocks by its counter digital Blocks. Harmonic oscillator (HO) is a mathematical implementation, facilitates generation of sinusoidal waveform, with adjustable frequency, amplitude and harmonics of Fundamental frequency with different phase shifts. It is a Fundamental Block for many communication systems and power control applications.This paper presents implementation of harmonic oscillator using different discretization techniques to test its stability. Most stable hybrid method is then used for generation of pulse width modulation (PWM) pulses, used in power control applications. Further using HO, an Amplitude Shift Keying (ASK) modulation system is implemented to witness its communication applications. HO simulation model is developed using Xilinx System Generator (XSG) in Matlab Simulink. Its VHDL simulation and synthesis is done to verify the functionality and identify the implementation resources required by various discretization methods. Hardware implementation is tested on Spartun-7 Field Programmable Gate Array (FPGA) platform.