The Experts below are selected from a list of 198 Experts worldwide ranked by ideXlab platform
G. Lowney - One of the best experts on this subject based on the ideXlab platform.
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ispike a post link optimizer for the intel spl reg itanium spl reg architecture
Symposium on Code Generation and Optimization, 2004Co-Authors: Robert Muth, Harish Patil, R. Cohn, G. LowneyAbstract:Ispike is a post-link optimizer developed for the Intel/spl reg/ Itanium Processor Family (IPF) processors. The IPF architecture poses both opportunities and challenges to post-link optimizations. IPF offers a rich set of performance counters to collect detailed profile information at a low cost, which is essential to post-link optimization being practical. At the same time, the predication and bundling features on IPF make post-link code transformation more challenging than on other architectures. In Ispike, we have implemented optimizations like code layout, instruction prefetching, data layout, and data prefetching that exploit the IPF advantages, and strategies that cope with the IPF-specific challenges. Using SPEC CINT2000 as benchmarks, we show that Ispike improves performance by as much as 40% on the ltanium/spl reg/2 processor, with average improvement of 8.5% and 9.9% over executables generated by the Intel/spl reg/ Electron Compiler and by the Gcc Compiler, respectively. We also demonstrate that statistical profiles collected via IPF performance counters and complete profiles collected via instrumentation produce equal performance benefit, but the profiling overhead is significantly lower for performance counters.
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ispike a post link optimizer for the intel itanium architecture
Symposium on Code Generation and Optimization, 2004Co-Authors: Robert Muth, Harish Patil, R. Cohn, G. LowneyAbstract:Ispike is post-link optimizer developed for theIntel®Itanium Processor Family (IPF) processors.TheIPF architecture poses both opportunities and challenges topost-link optimizations.IPF offers a rich set of performancecounters to collect detailed profile information at a low cost,which is essential to post-link optimization being practical.At the same time, the prediction and bundling features onIPF make post-link code transformation more challengingthan on other architectures.In Ispike, we have implementedoptimizations like code layout, instruction prefetching, datalayout, and data prefetching that exploit the IPF advantages,and strategies that cope with the IPF-specific challenges.Using SPEC CINT2000 as benchmarks, we showthat Ispike improves performance by as much as 40% on theItanium®2 processor, with average improvement of 8.5%and 9.9% over executables generated by the Intel®ElectronCompiler and by the Gcc Compiler, respectively.We alsodemonstrate that statistical profiles collected via IPF performancecounters and complete profiles collected via instrumentationproduce equal performance benefit, but theprofiling overhead is significantly lower for performancecounters.
Robert Muth - One of the best experts on this subject based on the ideXlab platform.
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ispike a post link optimizer for the intel spl reg itanium spl reg architecture
Symposium on Code Generation and Optimization, 2004Co-Authors: Robert Muth, Harish Patil, R. Cohn, G. LowneyAbstract:Ispike is a post-link optimizer developed for the Intel/spl reg/ Itanium Processor Family (IPF) processors. The IPF architecture poses both opportunities and challenges to post-link optimizations. IPF offers a rich set of performance counters to collect detailed profile information at a low cost, which is essential to post-link optimization being practical. At the same time, the predication and bundling features on IPF make post-link code transformation more challenging than on other architectures. In Ispike, we have implemented optimizations like code layout, instruction prefetching, data layout, and data prefetching that exploit the IPF advantages, and strategies that cope with the IPF-specific challenges. Using SPEC CINT2000 as benchmarks, we show that Ispike improves performance by as much as 40% on the ltanium/spl reg/2 processor, with average improvement of 8.5% and 9.9% over executables generated by the Intel/spl reg/ Electron Compiler and by the Gcc Compiler, respectively. We also demonstrate that statistical profiles collected via IPF performance counters and complete profiles collected via instrumentation produce equal performance benefit, but the profiling overhead is significantly lower for performance counters.
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ispike a post link optimizer for the intel itanium architecture
Symposium on Code Generation and Optimization, 2004Co-Authors: Robert Muth, Harish Patil, R. Cohn, G. LowneyAbstract:Ispike is post-link optimizer developed for theIntel®Itanium Processor Family (IPF) processors.TheIPF architecture poses both opportunities and challenges topost-link optimizations.IPF offers a rich set of performancecounters to collect detailed profile information at a low cost,which is essential to post-link optimization being practical.At the same time, the prediction and bundling features onIPF make post-link code transformation more challengingthan on other architectures.In Ispike, we have implementedoptimizations like code layout, instruction prefetching, datalayout, and data prefetching that exploit the IPF advantages,and strategies that cope with the IPF-specific challenges.Using SPEC CINT2000 as benchmarks, we showthat Ispike improves performance by as much as 40% on theItanium®2 processor, with average improvement of 8.5%and 9.9% over executables generated by the Intel®ElectronCompiler and by the Gcc Compiler, respectively.We alsodemonstrate that statistical profiles collected via IPF performancecounters and complete profiles collected via instrumentationproduce equal performance benefit, but theprofiling overhead is significantly lower for performancecounters.
Harish Patil - One of the best experts on this subject based on the ideXlab platform.
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ispike a post link optimizer for the intel spl reg itanium spl reg architecture
Symposium on Code Generation and Optimization, 2004Co-Authors: Robert Muth, Harish Patil, R. Cohn, G. LowneyAbstract:Ispike is a post-link optimizer developed for the Intel/spl reg/ Itanium Processor Family (IPF) processors. The IPF architecture poses both opportunities and challenges to post-link optimizations. IPF offers a rich set of performance counters to collect detailed profile information at a low cost, which is essential to post-link optimization being practical. At the same time, the predication and bundling features on IPF make post-link code transformation more challenging than on other architectures. In Ispike, we have implemented optimizations like code layout, instruction prefetching, data layout, and data prefetching that exploit the IPF advantages, and strategies that cope with the IPF-specific challenges. Using SPEC CINT2000 as benchmarks, we show that Ispike improves performance by as much as 40% on the ltanium/spl reg/2 processor, with average improvement of 8.5% and 9.9% over executables generated by the Intel/spl reg/ Electron Compiler and by the Gcc Compiler, respectively. We also demonstrate that statistical profiles collected via IPF performance counters and complete profiles collected via instrumentation produce equal performance benefit, but the profiling overhead is significantly lower for performance counters.
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ispike a post link optimizer for the intel itanium architecture
Symposium on Code Generation and Optimization, 2004Co-Authors: Robert Muth, Harish Patil, R. Cohn, G. LowneyAbstract:Ispike is post-link optimizer developed for theIntel®Itanium Processor Family (IPF) processors.TheIPF architecture poses both opportunities and challenges topost-link optimizations.IPF offers a rich set of performancecounters to collect detailed profile information at a low cost,which is essential to post-link optimization being practical.At the same time, the prediction and bundling features onIPF make post-link code transformation more challengingthan on other architectures.In Ispike, we have implementedoptimizations like code layout, instruction prefetching, datalayout, and data prefetching that exploit the IPF advantages,and strategies that cope with the IPF-specific challenges.Using SPEC CINT2000 as benchmarks, we showthat Ispike improves performance by as much as 40% on theItanium®2 processor, with average improvement of 8.5%and 9.9% over executables generated by the Intel®ElectronCompiler and by the Gcc Compiler, respectively.We alsodemonstrate that statistical profiles collected via IPF performancecounters and complete profiles collected via instrumentationproduce equal performance benefit, but theprofiling overhead is significantly lower for performancecounters.
R. Cohn - One of the best experts on this subject based on the ideXlab platform.
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ispike a post link optimizer for the intel spl reg itanium spl reg architecture
Symposium on Code Generation and Optimization, 2004Co-Authors: Robert Muth, Harish Patil, R. Cohn, G. LowneyAbstract:Ispike is a post-link optimizer developed for the Intel/spl reg/ Itanium Processor Family (IPF) processors. The IPF architecture poses both opportunities and challenges to post-link optimizations. IPF offers a rich set of performance counters to collect detailed profile information at a low cost, which is essential to post-link optimization being practical. At the same time, the predication and bundling features on IPF make post-link code transformation more challenging than on other architectures. In Ispike, we have implemented optimizations like code layout, instruction prefetching, data layout, and data prefetching that exploit the IPF advantages, and strategies that cope with the IPF-specific challenges. Using SPEC CINT2000 as benchmarks, we show that Ispike improves performance by as much as 40% on the ltanium/spl reg/2 processor, with average improvement of 8.5% and 9.9% over executables generated by the Intel/spl reg/ Electron Compiler and by the Gcc Compiler, respectively. We also demonstrate that statistical profiles collected via IPF performance counters and complete profiles collected via instrumentation produce equal performance benefit, but the profiling overhead is significantly lower for performance counters.
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ispike a post link optimizer for the intel itanium architecture
Symposium on Code Generation and Optimization, 2004Co-Authors: Robert Muth, Harish Patil, R. Cohn, G. LowneyAbstract:Ispike is post-link optimizer developed for theIntel®Itanium Processor Family (IPF) processors.TheIPF architecture poses both opportunities and challenges topost-link optimizations.IPF offers a rich set of performancecounters to collect detailed profile information at a low cost,which is essential to post-link optimization being practical.At the same time, the prediction and bundling features onIPF make post-link code transformation more challengingthan on other architectures.In Ispike, we have implementedoptimizations like code layout, instruction prefetching, datalayout, and data prefetching that exploit the IPF advantages,and strategies that cope with the IPF-specific challenges.Using SPEC CINT2000 as benchmarks, we showthat Ispike improves performance by as much as 40% on theItanium®2 processor, with average improvement of 8.5%and 9.9% over executables generated by the Intel®ElectronCompiler and by the Gcc Compiler, respectively.We alsodemonstrate that statistical profiles collected via IPF performancecounters and complete profiles collected via instrumentationproduce equal performance benefit, but theprofiling overhead is significantly lower for performancecounters.
Mohammad Amin Alipour - One of the best experts on this subject based on the ideXlab platform.
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configuring test generators using bug reports a case study of Gcc Compiler and csmith
ACM Symposium on Applied Computing, 2021Co-Authors: Rafiqul Islam Rabin, Mohammad Amin AlipourAbstract:The correctness of Compilers is instrumental in the safety and reliability of other software systems, as bugs in Compilers can produce executables that do not reflect the intent of programmers. Such errors are difficult to identify and debug. Random test program generators are commonly used in testing Compilers, and they have been effective in uncovering bugs. However, the problem of guiding these test generators to produce test programs that are more likely to find bugs remains challenging. In this paper, we use the code snippets in the bug reports to guide the test generation. The main idea of this work is to extract insights from the bug reports about the language features that are more prone to inadequate implementation and using the insights to guide the test generators. We use the Gcc C Compiler to evaluate the effectiveness of this approach. In particular, we first cluster the test programs in the Gcc bugs reports based on their features. We then use the centroids of the clusters to compute configurations for Csmith, a popular test generator for C Compilers. We evaluated this approach on eight versions of Gcc and found that our approach provides higher coverage and triggers more miscompilation failures than the state-of-the-art test generation techniques for Gcc.
