The Experts below are selected from a list of 117 Experts worldwide ranked by ideXlab platform
Dan Meng - One of the best experts on this subject based on the ideXlab platform.
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ICCS (3) - A Deep Malware Detection Method Based on General-Purpose Register Features
Lecture Notes in Computer Science, 2019Co-Authors: Chao Yan, Ziyuan Zhu, Dan MengAbstract:Based on low-level features at micro-architecture level, the existing detection methods usually need a long sample length to detect malicious behaviours and can hardly identify non-signature malware, which will inevitably affect the detection efficiency and effectiveness. To solve the above problems, we propose to use the General-Purpose Registers (GPRs) as our features and design a novel deep learning model for malware detection. Specifically, each Register has specific functions and changes of its content contain the action information which can be used to detect illegal behaviours. Also, we design a deep detection model, which can jointly fuse spatial and temporal correlations of GPRs for malware detection only requiring a short sample length. The proposed deep detection model can well learn discriminative characteristics from GPRs between normal and abnormal processes, and thus can also identify non-signature malware. Comprehensive experimental results show that our proposed method performs better than the state-of-art methods for malicious behaviours detection relying on low-level features.
Hyeokdong Kwon - One of the best experts on this subject based on the ideXlab platform.
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WISA - Compact LEA and HIGHT Implementations on 8-Bit AVR and 16-Bit MSP Processors
Information Security Applications, 2019Co-Authors: Hwajeong Seo, Hyeokdong KwonAbstract:In this paper, we revisited the previous LEA and HIGHT implementations on the low-end embedded processors. First, the general purpose Registers are fully utilized to cache the intermediate results of delta variable during key scheduling process of LEA. By caching the delta variables, the number of memory access is replaced to the relatively cheap Register access. Similarly, the master key and plaintext are cached during key scheduling and encryption of HIGHT block cipher, respectively. Second, stack storage and pointer are fully utilized to store the intermediate results and access the round keys. This approach solves the limited storage problem and saves one general purpose Register. Third, indirect addressing mode is more efficient than indexed addressing mode. In the decryption process of LEA, the round key pair is efficiently accessed through indirect addressing with minor address modification. Fourth, 8-bit word operations for HIGHT is efficiently handled by 16-bit wise instruction of 16-bit MSP processors. Finally, the proposed LEA implementations on the representative 8-bit AVR and 16-bit MSP processors are fully evaluated in terms of code size, RAM and execution timing. The proposed implementations over the target processors (8-bit AVR processor, 16-bit MSP processor) are faster than previous works by (13.6%, 9.3%), (0.6%, 8.5%), and (3.4%, 1.5%) for key scheduling, encryption, and decryption, respectively. Similarly, the proposed HIGHT implementations on the 16-bit MSP processors are faster than previous works by 38.6%, 33.7%, and 33.6% for key scheduling, encryption, and decryption, respectively.
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Compact LEA and HIGHT Implementations on 8-Bit AVR and 16-Bit MSP Processors
Information Security Applications, 2019Co-Authors: Hwajeong Seo, Kyuhwang An, Hyeokdong KwonAbstract:In this paper, we revisited the previous LEA and HIGHT implementations on the low-end embedded processors. First, the general purpose Registers are fully utilized to cache the intermediate results of delta variable during key scheduling process of LEA. By caching the delta variables, the number of memory access is replaced to the relatively cheap Register access. Similarly, the master key and plaintext are cached during key scheduling and encryption of HIGHT block cipher, respectively. Second, stack storage and pointer are fully utilized to store the intermediate results and access the round keys. This approach solves the limited storage problem and saves one general purpose Register. Third, indirect addressing mode is more efficient than indexed addressing mode. In the decryption process of LEA, the round key pair is efficiently accessed through indirect addressing with minor address modification. Fourth, 8-bit word operations for HIGHT is efficiently handled by 16-bit wise instruction of 16-bit MSP processors. Finally, the proposed LEA implementations on the representative 8-bit AVR and 16-bit MSP processors are fully evaluated in terms of code size, RAM and execution timing. The proposed implementations over the target processors (8-bit AVR processor, 16-bit MSP processor) are faster than previous works by (13.6%, 9.3%), (0.6%, 8.5%), and (3.4%, 1.5%) for key scheduling, encryption, and decryption, respectively. Similarly, the proposed HIGHT implementations on the 16-bit MSP processors are faster than previous works by 38.6%, 33.7%, and 33.6% for key scheduling, encryption, and decryption, respectively.
James E Smith - One of the best experts on this subject based on the ideXlab platform.
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an instruction set and microarchitecture for instruction level distributed processing
International Symposium on Computer Architecture, 2002Co-Authors: Hoseop Kim, James E SmithAbstract:An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical Register files with a small number of accumulators at the top. The instruction stream is divided into chains of dependent instructions (strands) where intra-strand dependences are passed through the accumulator. The General-Purpose Register file is used for communication between strands and for holding global values that have many consumers.A microarchitecture to support the proposed ISA is proposed and evaluated. The microarchitecture consists of multiple, distributed processing elements. Each PE contains an instruction issue FIFO, a local Register (accumulator) and local copy of Register file. The overall simplicity, hierarchical value communication, and distributed implementation will provide a very high clock speed and a relatively short pipeline while maintaining a form of superscalar out-of-order execution.Detailed timing simulations using translated program traces show the proposed microarchitecture is tolerant of global wire latencies. Ignoring the significant clock frequency advantages, a microarchitecture that supports a 4-wide fetch/decode pipeline, 8 serial PEs, and a two-cycle inter-PE communication latency performs as well as a conventional 4-way out-of-order superscalar processor.
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An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
2002Co-Authors: Hoseop Kim, James E SmithAbstract:An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical Register files with a small number of accumulators at the top. The instruction stream is divided into chains of dependent instructions (strands) where intra -strand dependences are passed through the accumulator. The General-Purpose Register file is used for communication between strands and for holding global values that have many consumers
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ISCA - An instruction set and microarchitecture for instruction level distributed processing
ACM SIGARCH Computer Architecture News, 2002Co-Authors: Hoseop Kim, James E SmithAbstract:An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical Register files with a small number of accumulators at the top. The instruction stream is divided into chains of dependent instructions (strands) where intra-strand dependences are passed through the accumulator. The General-Purpose Register file is used for communication between strands and for holding global values that have many consumers.A microarchitecture to support the proposed ISA is proposed and evaluated. The microarchitecture consists of multiple, distributed processing elements. Each PE contains an instruction issue FIFO, a local Register (accumulator) and local copy of Register file. The overall simplicity, hierarchical value communication, and distributed implementation will provide a very high clock speed and a relatively short pipeline while maintaining a form of superscalar out-of-order execution.Detailed timing simulations using translated program traces show the proposed microarchitecture is tolerant of global wire latencies. Ignoring the significant clock frequency advantages, a microarchitecture that supports a 4-wide fetch/decode pipeline, 8 serial PEs, and a two-cycle inter-PE communication latency performs as well as a conventional 4-way out-of-order superscalar processor.
Chao Yan - One of the best experts on this subject based on the ideXlab platform.
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ICCS (3) - A Deep Malware Detection Method Based on General-Purpose Register Features
Lecture Notes in Computer Science, 2019Co-Authors: Chao Yan, Ziyuan Zhu, Dan MengAbstract:Based on low-level features at micro-architecture level, the existing detection methods usually need a long sample length to detect malicious behaviours and can hardly identify non-signature malware, which will inevitably affect the detection efficiency and effectiveness. To solve the above problems, we propose to use the General-Purpose Registers (GPRs) as our features and design a novel deep learning model for malware detection. Specifically, each Register has specific functions and changes of its content contain the action information which can be used to detect illegal behaviours. Also, we design a deep detection model, which can jointly fuse spatial and temporal correlations of GPRs for malware detection only requiring a short sample length. The proposed deep detection model can well learn discriminative characteristics from GPRs between normal and abnormal processes, and thus can also identify non-signature malware. Comprehensive experimental results show that our proposed method performs better than the state-of-art methods for malicious behaviours detection relying on low-level features.
Hwajeong Seo - One of the best experts on this subject based on the ideXlab platform.
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WISA - Compact LEA and HIGHT Implementations on 8-Bit AVR and 16-Bit MSP Processors
Information Security Applications, 2019Co-Authors: Hwajeong Seo, Hyeokdong KwonAbstract:In this paper, we revisited the previous LEA and HIGHT implementations on the low-end embedded processors. First, the general purpose Registers are fully utilized to cache the intermediate results of delta variable during key scheduling process of LEA. By caching the delta variables, the number of memory access is replaced to the relatively cheap Register access. Similarly, the master key and plaintext are cached during key scheduling and encryption of HIGHT block cipher, respectively. Second, stack storage and pointer are fully utilized to store the intermediate results and access the round keys. This approach solves the limited storage problem and saves one general purpose Register. Third, indirect addressing mode is more efficient than indexed addressing mode. In the decryption process of LEA, the round key pair is efficiently accessed through indirect addressing with minor address modification. Fourth, 8-bit word operations for HIGHT is efficiently handled by 16-bit wise instruction of 16-bit MSP processors. Finally, the proposed LEA implementations on the representative 8-bit AVR and 16-bit MSP processors are fully evaluated in terms of code size, RAM and execution timing. The proposed implementations over the target processors (8-bit AVR processor, 16-bit MSP processor) are faster than previous works by (13.6%, 9.3%), (0.6%, 8.5%), and (3.4%, 1.5%) for key scheduling, encryption, and decryption, respectively. Similarly, the proposed HIGHT implementations on the 16-bit MSP processors are faster than previous works by 38.6%, 33.7%, and 33.6% for key scheduling, encryption, and decryption, respectively.
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Compact LEA and HIGHT Implementations on 8-Bit AVR and 16-Bit MSP Processors
Information Security Applications, 2019Co-Authors: Hwajeong Seo, Kyuhwang An, Hyeokdong KwonAbstract:In this paper, we revisited the previous LEA and HIGHT implementations on the low-end embedded processors. First, the general purpose Registers are fully utilized to cache the intermediate results of delta variable during key scheduling process of LEA. By caching the delta variables, the number of memory access is replaced to the relatively cheap Register access. Similarly, the master key and plaintext are cached during key scheduling and encryption of HIGHT block cipher, respectively. Second, stack storage and pointer are fully utilized to store the intermediate results and access the round keys. This approach solves the limited storage problem and saves one general purpose Register. Third, indirect addressing mode is more efficient than indexed addressing mode. In the decryption process of LEA, the round key pair is efficiently accessed through indirect addressing with minor address modification. Fourth, 8-bit word operations for HIGHT is efficiently handled by 16-bit wise instruction of 16-bit MSP processors. Finally, the proposed LEA implementations on the representative 8-bit AVR and 16-bit MSP processors are fully evaluated in terms of code size, RAM and execution timing. The proposed implementations over the target processors (8-bit AVR processor, 16-bit MSP processor) are faster than previous works by (13.6%, 9.3%), (0.6%, 8.5%), and (3.4%, 1.5%) for key scheduling, encryption, and decryption, respectively. Similarly, the proposed HIGHT implementations on the 16-bit MSP processors are faster than previous works by 38.6%, 33.7%, and 33.6% for key scheduling, encryption, and decryption, respectively.