The Experts below are selected from a list of 81306 Experts worldwide ranked by ideXlab platform

Shekhar Borkar - One of the best experts on this subject based on the ideXlab platform.

  • a 4 ghz 130 nm address Generation Unit with 32 bit sparse tree adder core
    IEEE Journal of Solid-state Circuits, 2003
    Co-Authors: Sanu K Mathew, Mark A Anders, Ram Krishnamurthy, Shekhar Borkar
    Abstract:

    This paper describes a 32-bit address Generation Unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-V/sub T/ semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm scaling trend.

  • a 4 ghz 130 nm address Generation Unit with 32 bit sparse tree adder core
    Symposium on VLSI Circuits, 2002
    Co-Authors: Sanu K Mathew, Mark A Anders, Ram Krishnamurthy, Shekhar Borkar
    Abstract:

    This paper describes a 32-bit Address Generation Unit (AGU) designed for 4 GHz operation in 1.2 V, 130 nm technology. The AGU utilizes a 152 ps dual-V, sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect density and a low (1%) active energy leakage component. The semidynamic implementation enables an average energy profile similar to static CMOS, with good sub-130 nm scaling trend.

Sanu K Mathew - One of the best experts on this subject based on the ideXlab platform.

  • a 4 ghz 130 nm address Generation Unit with 32 bit sparse tree adder core
    IEEE Journal of Solid-state Circuits, 2003
    Co-Authors: Sanu K Mathew, Mark A Anders, Ram Krishnamurthy, Shekhar Borkar
    Abstract:

    This paper describes a 32-bit address Generation Unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-V/sub T/ semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm scaling trend.

  • a 4 ghz 130 nm address Generation Unit with 32 bit sparse tree adder core
    Symposium on VLSI Circuits, 2002
    Co-Authors: Sanu K Mathew, Mark A Anders, Ram Krishnamurthy, Shekhar Borkar
    Abstract:

    This paper describes a 32-bit Address Generation Unit (AGU) designed for 4 GHz operation in 1.2 V, 130 nm technology. The AGU utilizes a 152 ps dual-V, sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect density and a low (1%) active energy leakage component. The semidynamic implementation enables an average energy profile similar to static CMOS, with good sub-130 nm scaling trend.

Wei Huang - One of the best experts on this subject based on the ideXlab platform.

  • highly efficient tandem organic light emitting devices adopting a nondoped charge Generation Unit and ultrathin emitting layers
    Organic Electronics, 2018
    Co-Authors: Xinwen Zhang, Mengke Zhang, Mengjiao Liu, Yuehua Chen, Jiong Wang, Xiaolin Zhang, Junjie Zhang, Wenyong Lai, Wei Huang
    Abstract:

    Abstract Highly efficient non-doped tandem phosphorescent organic light-emitting devices (PhOLEDs) have been demonstrated by employing LiF/AL/1,4,5,8,9,11-hexaazatriphenylene hexacarbonitrile (HAT-CN) as a charge Generation Unit (CGU) and ultrathin phosphorescent dyes as emitting layers (EMLs). It was found that the performance of the tandem PhOLEDs was significantly dependent on the Al thickness in CGU. Analyses regarding the current density-voltage characteristics of the CGU only devices indicate that the charge carriers are generated at the HAT-CN/NPB interface, and Al/LiF layers work as assistant electron injection layers to facilitate electron extraction from CGU and injection into the adjacent electron transport layer. From the capacitance-voltage and optical transparency characteristics of CGU with different thicknesses of Al interlayer, the thick Al layer is beneficial to charge separation, while it weakens the light output of the tandem device. Under the optimal Al thickness of 5 nm, more than twofold enhancement of current efficiency is achieved for the non-doped tandem blue device. Furthermore, the non-doped tandem white PhOLED was also developed showing a maximum current efficiency of 94.9 cd/A and maximum external quantum efficiency of 31.6%.

Hirokuni Hachiuma - One of the best experts on this subject based on the ideXlab platform.

  • Study of Thermoelectric Generation Unit for Radiant Waste Heat
    Materials Today: Proceedings, 2015
    Co-Authors: Takeshi Kajihara, Yong Hoon Lee, Kazuya Makino, Hiromasa Kaibe, Hirokuni Hachiuma
    Abstract:

    Thermoelectric Generation technology is a promising technology which converts the industrial process waste heat energy to useful electrical energy. Using thermoelectric Generation Unit which consists of several thermoelectric Generation modules, verification experiments have been held at some industrial process. In this paper, the output power and thermal performance of the thermoelectric Generation Unit are described in radiant waste heat recovery. The output power of thermoelectric Generation Unit depends on thermoelectric element size and number. We discuss the optimum performance for various sizes and number of thermoelectric elements in practical thermoelectric Generation Unit. Also, the comparison of Generation performance of thermoelectric Generation Unit using Bi-Te material and high temperature thermoelectric material is discussed.

Ram Krishnamurthy - One of the best experts on this subject based on the ideXlab platform.

  • a 4 ghz 130 nm address Generation Unit with 32 bit sparse tree adder core
    IEEE Journal of Solid-state Circuits, 2003
    Co-Authors: Sanu K Mathew, Mark A Anders, Ram Krishnamurthy, Shekhar Borkar
    Abstract:

    This paper describes a 32-bit address Generation Unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-V/sub T/ semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm scaling trend.

  • a 4 ghz 130 nm address Generation Unit with 32 bit sparse tree adder core
    Symposium on VLSI Circuits, 2002
    Co-Authors: Sanu K Mathew, Mark A Anders, Ram Krishnamurthy, Shekhar Borkar
    Abstract:

    This paper describes a 32-bit Address Generation Unit (AGU) designed for 4 GHz operation in 1.2 V, 130 nm technology. The AGU utilizes a 152 ps dual-V, sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect density and a low (1%) active energy leakage component. The semidynamic implementation enables an average energy profile similar to static CMOS, with good sub-130 nm scaling trend.