The Experts below are selected from a list of 33 Experts worldwide ranked by ideXlab platform
Huang Jun - One of the best experts on this subject based on the ideXlab platform.
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Gigabit Ethernet Port auto-negotiation analysis
Optical Communication Technology, 2009Co-Authors: Huang JunAbstract:To realize the hybrid communication of different rates Ethernet devices since the Ethernet devel-oped to the Fast Ethernet,on the basis of describing the fundamental principle of Ethernet Auto-negotiation,illustrates the three page frames structure of GB Ethernet Auto-negotiation.The process of GB Ethernet Au-to-negotiation is emphasized,and introduces the Auto-negotiation receiving and transmitting process of GB Ethernet Ports individually take the 1000BASE-T for example
Ulrich Rueckert - One of the best experts on this subject based on the ideXlab platform.
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ReConFig - A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms
2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015Co-Authors: Omar W. Ibraheem, Arif Irwansyah, Jens Hagemeyer, Mario Porrmann, Ulrich RueckertAbstract:In vision processing systems, many applications require multi-camera supPort. For the connection of the cameras to the processing system, multiple interfaces and a platform capable of handling sustained high data rates are essential. To cope with these requirements, a hardware-based solution using FPGA technology is advisable, especially when targeting space and energy constrained embedded systems. The aim of this work is to develop and implement an FPGA-based scalable and resourceefficient multi-camera GigE Vision IP core for video and image processing. To reduce the number of interfaces needed, the IP core supPorts the connection of multi-camera interfaces to a single Gigabit Ethernet Port using an Ethernet switch. The multicamera GigE Vision IP core is able to extract the raw video data from multiple GigE Vision video streams, reconstruct the video frames from every camera and pass these data for further processing. To test the system, four GigE Vision cameras are used. The IP core is implemented on a Xilinx Virtex-4 FPGA and integrated in a complete video processing platform for a full system realization. In addition to the IP core, bilinear interpolation for image demosaicing with Bayer pattern and an automatic white balance algorithm are implemented for evaluation of the platform. Benchmarking of the hardware implementation has been performed with a total resolution of up to 2048x2048 pixels. Achieved frame rates vary from 25 fps to 345 fps depending on the selected resolution and on the number of used cameras.
Omar W. Ibraheem - One of the best experts on this subject based on the ideXlab platform.
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ReConFig - A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms
2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015Co-Authors: Omar W. Ibraheem, Arif Irwansyah, Jens Hagemeyer, Mario Porrmann, Ulrich RueckertAbstract:In vision processing systems, many applications require multi-camera supPort. For the connection of the cameras to the processing system, multiple interfaces and a platform capable of handling sustained high data rates are essential. To cope with these requirements, a hardware-based solution using FPGA technology is advisable, especially when targeting space and energy constrained embedded systems. The aim of this work is to develop and implement an FPGA-based scalable and resourceefficient multi-camera GigE Vision IP core for video and image processing. To reduce the number of interfaces needed, the IP core supPorts the connection of multi-camera interfaces to a single Gigabit Ethernet Port using an Ethernet switch. The multicamera GigE Vision IP core is able to extract the raw video data from multiple GigE Vision video streams, reconstruct the video frames from every camera and pass these data for further processing. To test the system, four GigE Vision cameras are used. The IP core is implemented on a Xilinx Virtex-4 FPGA and integrated in a complete video processing platform for a full system realization. In addition to the IP core, bilinear interpolation for image demosaicing with Bayer pattern and an automatic white balance algorithm are implemented for evaluation of the platform. Benchmarking of the hardware implementation has been performed with a total resolution of up to 2048x2048 pixels. Achieved frame rates vary from 25 fps to 345 fps depending on the selected resolution and on the number of used cameras.
Takao Onoye - One of the best experts on this subject based on the ideXlab platform.
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GCCE - Multi-eyed network camera for convenient 3D video capturing
2014 IEEE 3rd Global Conference on Consumer Electronics (GCCE), 2014Co-Authors: Kazuhito Sakomizu, Takashi Nishi, Takao OnoyeAbstract:To capture and record a multi-view video is inconvenient due to needing mechanism for synchronization between cameras and computational cost for video coding. This paper presents a multi-eyed network camera which has five fixed HD camera modules and a Gigabit Ethernet Port. Only one LSI controls the camera modules and encodes all captured videos. To reduce computational complexity and keep synchronization, compressing is based on distributed video coding, and multiplexing is an extension format of the H. 264/MVC NAL structure. Implementation results show that all functions are integrated in the LSI and that the synchronization is kept after transmitting.
Mario Porrmann - One of the best experts on this subject based on the ideXlab platform.
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ReConFig - A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms
2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015Co-Authors: Omar W. Ibraheem, Arif Irwansyah, Jens Hagemeyer, Mario Porrmann, Ulrich RueckertAbstract:In vision processing systems, many applications require multi-camera supPort. For the connection of the cameras to the processing system, multiple interfaces and a platform capable of handling sustained high data rates are essential. To cope with these requirements, a hardware-based solution using FPGA technology is advisable, especially when targeting space and energy constrained embedded systems. The aim of this work is to develop and implement an FPGA-based scalable and resourceefficient multi-camera GigE Vision IP core for video and image processing. To reduce the number of interfaces needed, the IP core supPorts the connection of multi-camera interfaces to a single Gigabit Ethernet Port using an Ethernet switch. The multicamera GigE Vision IP core is able to extract the raw video data from multiple GigE Vision video streams, reconstruct the video frames from every camera and pass these data for further processing. To test the system, four GigE Vision cameras are used. The IP core is implemented on a Xilinx Virtex-4 FPGA and integrated in a complete video processing platform for a full system realization. In addition to the IP core, bilinear interpolation for image demosaicing with Bayer pattern and an automatic white balance algorithm are implemented for evaluation of the platform. Benchmarking of the hardware implementation has been performed with a total resolution of up to 2048x2048 pixels. Achieved frame rates vary from 25 fps to 345 fps depending on the selected resolution and on the number of used cameras.