The Experts below are selected from a list of 303 Experts worldwide ranked by ideXlab platform
Tim Teitelbaum - One of the best experts on this subject based on the ideXlab platform.
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program slicing of Hardware Description Languages
Lecture Notes in Computer Science, 1999Co-Authors: Edmund M Clarke, Masahiro Fujita, Sreeranga P Rajan, Thomas Reps, Subash Shankar, Tim TeitelbaumAbstract:Hardware Description Languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a Description of the resulting tool, and a brief overview of some applications and experimental results.
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CHARME - Program Slicing of Hardware Description Languages
Lecture Notes in Computer Science, 1999Co-Authors: Edmund M Clarke, Masahiro Fujita, Sreeranga P Rajan, Thomas Reps, Subash Shankar, Tim TeitelbaumAbstract:Hardware Description Languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a Description of the resulting tool, and a brief overview of some applications and experimental results.
Subash Shankar - One of the best experts on this subject based on the ideXlab platform.
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program slicing of Hardware Description Languages
Lecture Notes in Computer Science, 1999Co-Authors: Edmund M Clarke, Masahiro Fujita, Sreeranga P Rajan, Thomas Reps, Subash Shankar, Tim TeitelbaumAbstract:Hardware Description Languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a Description of the resulting tool, and a brief overview of some applications and experimental results.
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CHARME - Program Slicing of Hardware Description Languages
Lecture Notes in Computer Science, 1999Co-Authors: Edmund M Clarke, Masahiro Fujita, Sreeranga P Rajan, Thomas Reps, Subash Shankar, Tim TeitelbaumAbstract:Hardware Description Languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a Description of the resulting tool, and a brief overview of some applications and experimental results.
Edmund M Clarke - One of the best experts on this subject based on the ideXlab platform.
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program slicing of Hardware Description Languages
Lecture Notes in Computer Science, 1999Co-Authors: Edmund M Clarke, Masahiro Fujita, Sreeranga P Rajan, Thomas Reps, Subash Shankar, Tim TeitelbaumAbstract:Hardware Description Languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a Description of the resulting tool, and a brief overview of some applications and experimental results.
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CHARME - Program Slicing of Hardware Description Languages
Lecture Notes in Computer Science, 1999Co-Authors: Edmund M Clarke, Masahiro Fujita, Sreeranga P Rajan, Thomas Reps, Subash Shankar, Tim TeitelbaumAbstract:Hardware Description Languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a Description of the resulting tool, and a brief overview of some applications and experimental results.
Zhichao Deng - One of the best experts on this subject based on the ideXlab platform.
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DAC - Modeling safe operating area in Hardware Description Languages
Proceedings of the 44th annual conference on Design automation - DAC '07, 2007Co-Authors: Leonid Goldgeisser, Ernst Christen, Zhichao DengAbstract:Creating a Robust Design requires that the operating conditions of each component of the design are carefully measured and compared with its Safe Operating, a task commonly referred to as stress analysis. In this paper we analyze the relationship between the component stress and the Safe Operating Area. We summarize the requirements of describing the Safe Operating Areas and propose how these requirements can be used to model the concept with two Hardware Description Languages: MASTreg and VHDL-AMS. A circuit example is given.
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modeling safe operating area in Hardware Description Languages
Design Automation Conference, 2007Co-Authors: Leonid Goldgeisser, Ernst Christen, Zhichao DengAbstract:Creating a Robust Design requires that the operating conditions of each component of the design are carefully measured and compared with its Safe Operating, a task commonly referred to as stress analysis. In this paper we analyze the relationship between the component stress and the Safe Operating Area. We summarize the requirements of describing the Safe Operating Areas and propose how these requirements can be used to model the concept with two Hardware Description Languages: MAST® and VHDL-AMS. A circuit example is given.
Masahiro Fujita - One of the best experts on this subject based on the ideXlab platform.
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program slicing of Hardware Description Languages
Lecture Notes in Computer Science, 1999Co-Authors: Edmund M Clarke, Masahiro Fujita, Sreeranga P Rajan, Thomas Reps, Subash Shankar, Tim TeitelbaumAbstract:Hardware Description Languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a Description of the resulting tool, and a brief overview of some applications and experimental results.
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CHARME - Program Slicing of Hardware Description Languages
Lecture Notes in Computer Science, 1999Co-Authors: Edmund M Clarke, Masahiro Fujita, Sreeranga P Rajan, Thomas Reps, Subash Shankar, Tim TeitelbaumAbstract:Hardware Description Languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a Description of the resulting tool, and a brief overview of some applications and experimental results.
