The Experts below are selected from a list of 93 Experts worldwide ranked by ideXlab platform
Mohit Tiwari - One of the best experts on this subject based on the ideXlab platform.
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DAC - Invited - Who is the major threat to tomorrow's security?: you, the Hardware Designer
Proceedings of the 53rd Annual Design Automation Conference, 2016Co-Authors: Wayne Burleson, Onur Mutlu, Mohit TiwariAbstract:More and more security attacks today are perpetrated by exploiting the Hardware: memory errors can be exploited to take over systems, side-channel attacks leak secrets to the outside worlds, weak random number generators render cryptography ineffective, etc. At the same time, many of the tenets of efficient design are in tension with guaranteeing security. For instance, classic secure Hardware does not allow to optimize common execution patterns, share resources, or provide deep introspection. We provide brief descriptions of three recently-exposed Hardware vulnerabilities along with extensive references for background and to learn more about these areas. Specifically, we first discuss the Rowhammer problem in modern DRAM chips, which enables attackers to circumvent memory isolation, and other potential vulnerabilities due to aggressive memory technology scaling. We next describe Hardware Trojans implemented below the gate level, which can resist most detection techniques, and other manufacturing vulnerabilities in security primitives. Finally, we explain side channels that can achieve very large information leakage capacities, and various potential defenses against them. We conclude by noting that the intersection of Hardware design and security attacks and countermeasures will continue to present a rich area for research and development for many years to come.
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invited who is the major threat to tomorrow s security you the Hardware Designer
Design Automation Conference, 2016Co-Authors: Wayne Burleson, Onur Mutlu, Mohit TiwariAbstract:More and more security attacks today are perpetrated by exploiting the Hardware: memory errors can be exploited to take over systems, side-channel attacks leak secrets to the outside worlds, weak random number generators render cryptography ineffective, etc. At the same time, many of the tenets of efficient design are in tension with guaranteeing security. For instance, classic secure Hardware does not allow to optimize common execution patterns, share resources, or provide deep introspection. We provide brief descriptions of three recently-exposed Hardware vulnerabilities along with extensive references for background and to learn more about these areas. Specifically, we first discuss the Rowhammer problem in modern DRAM chips, which enables attackers to circumvent memory isolation, and other potential vulnerabilities due to aggressive memory technology scaling. We next describe Hardware Trojans implemented below the gate level, which can resist most detection techniques, and other manufacturing vulnerabilities in security primitives. Finally, we explain side channels that can achieve very large information leakage capacities, and various potential defenses against them. We conclude by noting that the intersection of Hardware design and security attacks and countermeasures will continue to present a rich area for research and development for many years to come.
Wayne Burleson - One of the best experts on this subject based on the ideXlab platform.
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DAC - Invited - Who is the major threat to tomorrow's security?: you, the Hardware Designer
Proceedings of the 53rd Annual Design Automation Conference, 2016Co-Authors: Wayne Burleson, Onur Mutlu, Mohit TiwariAbstract:More and more security attacks today are perpetrated by exploiting the Hardware: memory errors can be exploited to take over systems, side-channel attacks leak secrets to the outside worlds, weak random number generators render cryptography ineffective, etc. At the same time, many of the tenets of efficient design are in tension with guaranteeing security. For instance, classic secure Hardware does not allow to optimize common execution patterns, share resources, or provide deep introspection. We provide brief descriptions of three recently-exposed Hardware vulnerabilities along with extensive references for background and to learn more about these areas. Specifically, we first discuss the Rowhammer problem in modern DRAM chips, which enables attackers to circumvent memory isolation, and other potential vulnerabilities due to aggressive memory technology scaling. We next describe Hardware Trojans implemented below the gate level, which can resist most detection techniques, and other manufacturing vulnerabilities in security primitives. Finally, we explain side channels that can achieve very large information leakage capacities, and various potential defenses against them. We conclude by noting that the intersection of Hardware design and security attacks and countermeasures will continue to present a rich area for research and development for many years to come.
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invited who is the major threat to tomorrow s security you the Hardware Designer
Design Automation Conference, 2016Co-Authors: Wayne Burleson, Onur Mutlu, Mohit TiwariAbstract:More and more security attacks today are perpetrated by exploiting the Hardware: memory errors can be exploited to take over systems, side-channel attacks leak secrets to the outside worlds, weak random number generators render cryptography ineffective, etc. At the same time, many of the tenets of efficient design are in tension with guaranteeing security. For instance, classic secure Hardware does not allow to optimize common execution patterns, share resources, or provide deep introspection. We provide brief descriptions of three recently-exposed Hardware vulnerabilities along with extensive references for background and to learn more about these areas. Specifically, we first discuss the Rowhammer problem in modern DRAM chips, which enables attackers to circumvent memory isolation, and other potential vulnerabilities due to aggressive memory technology scaling. We next describe Hardware Trojans implemented below the gate level, which can resist most detection techniques, and other manufacturing vulnerabilities in security primitives. Finally, we explain side channels that can achieve very large information leakage capacities, and various potential defenses against them. We conclude by noting that the intersection of Hardware design and security attacks and countermeasures will continue to present a rich area for research and development for many years to come.
Onur Mutlu - One of the best experts on this subject based on the ideXlab platform.
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DAC - Invited - Who is the major threat to tomorrow's security?: you, the Hardware Designer
Proceedings of the 53rd Annual Design Automation Conference, 2016Co-Authors: Wayne Burleson, Onur Mutlu, Mohit TiwariAbstract:More and more security attacks today are perpetrated by exploiting the Hardware: memory errors can be exploited to take over systems, side-channel attacks leak secrets to the outside worlds, weak random number generators render cryptography ineffective, etc. At the same time, many of the tenets of efficient design are in tension with guaranteeing security. For instance, classic secure Hardware does not allow to optimize common execution patterns, share resources, or provide deep introspection. We provide brief descriptions of three recently-exposed Hardware vulnerabilities along with extensive references for background and to learn more about these areas. Specifically, we first discuss the Rowhammer problem in modern DRAM chips, which enables attackers to circumvent memory isolation, and other potential vulnerabilities due to aggressive memory technology scaling. We next describe Hardware Trojans implemented below the gate level, which can resist most detection techniques, and other manufacturing vulnerabilities in security primitives. Finally, we explain side channels that can achieve very large information leakage capacities, and various potential defenses against them. We conclude by noting that the intersection of Hardware design and security attacks and countermeasures will continue to present a rich area for research and development for many years to come.
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invited who is the major threat to tomorrow s security you the Hardware Designer
Design Automation Conference, 2016Co-Authors: Wayne Burleson, Onur Mutlu, Mohit TiwariAbstract:More and more security attacks today are perpetrated by exploiting the Hardware: memory errors can be exploited to take over systems, side-channel attacks leak secrets to the outside worlds, weak random number generators render cryptography ineffective, etc. At the same time, many of the tenets of efficient design are in tension with guaranteeing security. For instance, classic secure Hardware does not allow to optimize common execution patterns, share resources, or provide deep introspection. We provide brief descriptions of three recently-exposed Hardware vulnerabilities along with extensive references for background and to learn more about these areas. Specifically, we first discuss the Rowhammer problem in modern DRAM chips, which enables attackers to circumvent memory isolation, and other potential vulnerabilities due to aggressive memory technology scaling. We next describe Hardware Trojans implemented below the gate level, which can resist most detection techniques, and other manufacturing vulnerabilities in security primitives. Finally, we explain side channels that can achieve very large information leakage capacities, and various potential defenses against them. We conclude by noting that the intersection of Hardware design and security attacks and countermeasures will continue to present a rich area for research and development for many years to come.
P M Grant - One of the best experts on this subject based on the ideXlab platform.
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Signal processing Hardware and software
Ieee Signal Processing Magazine, 1996Co-Authors: P M GrantAbstract:The explosive growth of digital signal processing techniques has given way to a myriad of high performance DSP devices and tools for today's Hardware Designer and software specialist. The charts and tables presented reflect up-to-date information on the most widely used programmable DSP chips, DSP board products, major software tools in wide use, types of commercial A-D converters, advanced A-D converters in research, available FIR filters (standard and weighted), IC frequency synthesizers, and integrated FFT chipsets
Jörn-marc Schmidt - One of the best experts on this subject based on the ideXlab platform.
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Hardware Designer's Guide to Fault Attacks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013Co-Authors: Dusko Karaklajic, Jörn-marc Schmidt, Ingrid VerbauwhedeAbstract:Hardware Designers invest a significant design effort when implementing computationally intensive cryptographic algorithms onto constrained embedded devices to match the computational demands of the algorithms with the stringent area, power, and energy budgets of the platforms. When it comes to designs that are employed in potential hostile environments, another challenge arises-the design has to be resistant against attacks based on the physical properties of the implementation, the so-called implementation attacks. This creates an extra design concern for a Hardware Designer. This paper gives an insight into the field of fault attacks and countermeasures to help the Designer to protect the design against this type of implementation attacks. We analyze fault attacks from different aspects and expose the mechanisms they employ to reveal a secret parameter of a device. In addition, we classify the existing countermeasures and discuss their effectiveness and efficiency. The result of this paper is a guide for selecting a set of countermeasures, which provides a sufficient security level to meet the constraints of the embedded devices.
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FDTC - The Fault Attack Jungle - A Classification Model to Guide You
2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011Co-Authors: Ingrid Verbauwhede, Dusko Karaklajic, Jörn-marc SchmidtAbstract:For a secure Hardware Designer, the vast array of fault attacks and countermeasures looks like a jungle. This paper aims at providing a guide through this jungle and at helping a Designer of secure embedded devices to protect a design in the most efficient way. We classify the existing fault attacks on implementations of cryptographic algorithms on embedded devices according to different criteria. By doing do, we expose possible security threats caused by fault attacks and propose different classes of countermeasures capable of preventing them.
