The Experts below are selected from a list of 26796 Experts worldwide ranked by ideXlab platform
Jizhong Zhao - One of the best experts on this subject based on the ideXlab platform.
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GenePrint: Generic and Accurate Physical-Layer Identification for UHF RFID Tags
IEEE/ACM Transactions on Networking, 2016Co-Authors: Jinsong Han, Zhiping Jiang, Panlong Yang, Dan Ma, Wei Xi, Chen Qian, Jizhong ZhaoAbstract:Physical-layer identification utilizes unique Features of wireless devices as their fingerprints, providing authenticity and security guarantee. Prior physical-layer identification techniques on radio frequency identification (RFID) tags require nongeneric equipments and are not fully compatible with existing standards. In this paper, we propose a novel physical-layer identification system, GenePrint, for UHF passive tags. The GenePrint prototype system is implemented by a commercial reader, a USRP-based monitor, and off-the-shelf UHF passive tags. Our solution is generic and completely compatible with the existing standard, EPCglobal C1G2 specification. GenePrint leverages the internal similarity among pulses of tags' RN16 preamble signals to extract a Hardware Feature as the fingerprint. We conduct extensive experiments on over 10 000 RN16 preamble signals from 150 off-the-shelf RFID tags. The results show that GenePrint achieves a high identification accuracy of 99.68% +. The Feature extraction of GenePrint is resilient to various malicious attacks, such as the Feature replay attack.
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ICNP - GenePrint: Generic and accurate physical-layer identification for UHF RFID tags
2013 21st IEEE International Conference on Network Protocols (ICNP), 2013Co-Authors: Chen Qian, Jinsong Han, Jizhong ZhaoAbstract:Physical-layer identification utilizes unique Features of wireless devices as their fingerprints, providing authenticity and security guarantee. Prior physical-layer identification techniques on RFID tags require non-generic equipments and are not fully compatible with existing standards. In this paper, we propose a novel physical-layer identification system, GenePrint, for UHF passive tags. The GenePrint prototype system is implemented by a commercial reader, a USRP-based monitor, and off-the-shelf UHF passive tags. Our solution is generic and completely compatible with the existing standard, EPCglobal C1G2 specification. GenePrint leverages the internal similarity among the pulses of tags' RN16 preamble signals to extract a Hardware Feature as the fingerprint. We conduct extensive experiments on over 10,000 RN16 preamble signals from 150 off-the-shelf RFID tags. The results show that GenePrint achieves a high identification accuracy of 99.68%+. The Feature extraction of GenePrint is resilient to various malicious attacks, such as the Feature replay attack.
Taesun Chung - One of the best experts on this subject based on the ideXlab platform.
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CSE/EUC/DCABES - Request-Size Aware Flash Translation Layer Based on Page-Level Mapping
2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th , 2016Co-Authors: Joon-young Paik, Taesun ChungAbstract:As more and more flash memory technologies quickly improve, NAND flash memory storage system has become more and more used as a non-volatile storage for embedded applications such as smart phones, smart watch, digital camera and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. However, the flash storage system does not perform well because of their Hardware Feature and the cost of garbage collection. To overcome this limitations, in this paper we provide a novel page mapping scheme named Request-Size aware Flash Translation Layer (RSaFTL) based on the page-level mapping algorithm. Our FTL is designed to reduce garbage collection overhead by using characteristics of overwriting one-page-unit data in flash memory. Experimental results show that RSaFTL outperforms the pure page mapping scheme by up to 29.4% on write-intensive workload with no addition RAM resource.
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CSE/EUC/DCABES - Request-Size Aware Flash Translation Layer Based on Page-Level Mapping
2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th , 2016Co-Authors: Joon-young Paik, Taesun ChungAbstract:As more and more flash memory technologies quickly improve, NAND flash memory storage system has become more and more used as a non-volatile storage for embedded applications such as smart phones, smart watch, digital camera and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. However, the flash storage system does not perform well because of their Hardware Feature and the cost of garbage collection. To overcome this limitations, in this paper we provide a novel page mapping scheme named Request-Size aware Flash Translation Layer (RSaFTL) based on the page-level mapping algorithm. Our FTL is designed to reduce garbage collection overhead by using characteristics of overwriting one-page-unit data in flash memory. Experimental results show that RSaFTL outperforms the pure page mapping scheme by up to 29.4% on write-intensive workload with no addition RAM resource.
Chen Qian - One of the best experts on this subject based on the ideXlab platform.
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GenePrint: Generic and Accurate Physical-Layer Identification for UHF RFID Tags
IEEE/ACM Transactions on Networking, 2016Co-Authors: Jinsong Han, Zhiping Jiang, Panlong Yang, Dan Ma, Wei Xi, Chen Qian, Jizhong ZhaoAbstract:Physical-layer identification utilizes unique Features of wireless devices as their fingerprints, providing authenticity and security guarantee. Prior physical-layer identification techniques on radio frequency identification (RFID) tags require nongeneric equipments and are not fully compatible with existing standards. In this paper, we propose a novel physical-layer identification system, GenePrint, for UHF passive tags. The GenePrint prototype system is implemented by a commercial reader, a USRP-based monitor, and off-the-shelf UHF passive tags. Our solution is generic and completely compatible with the existing standard, EPCglobal C1G2 specification. GenePrint leverages the internal similarity among pulses of tags' RN16 preamble signals to extract a Hardware Feature as the fingerprint. We conduct extensive experiments on over 10 000 RN16 preamble signals from 150 off-the-shelf RFID tags. The results show that GenePrint achieves a high identification accuracy of 99.68% +. The Feature extraction of GenePrint is resilient to various malicious attacks, such as the Feature replay attack.
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ICNP - GenePrint: Generic and accurate physical-layer identification for UHF RFID tags
2013 21st IEEE International Conference on Network Protocols (ICNP), 2013Co-Authors: Chen Qian, Jinsong Han, Jizhong ZhaoAbstract:Physical-layer identification utilizes unique Features of wireless devices as their fingerprints, providing authenticity and security guarantee. Prior physical-layer identification techniques on RFID tags require non-generic equipments and are not fully compatible with existing standards. In this paper, we propose a novel physical-layer identification system, GenePrint, for UHF passive tags. The GenePrint prototype system is implemented by a commercial reader, a USRP-based monitor, and off-the-shelf UHF passive tags. Our solution is generic and completely compatible with the existing standard, EPCglobal C1G2 specification. GenePrint leverages the internal similarity among the pulses of tags' RN16 preamble signals to extract a Hardware Feature as the fingerprint. We conduct extensive experiments on over 10,000 RN16 preamble signals from 150 off-the-shelf RFID tags. The results show that GenePrint achieves a high identification accuracy of 99.68%+. The Feature extraction of GenePrint is resilient to various malicious attacks, such as the Feature replay attack.
Joon-young Paik - One of the best experts on this subject based on the ideXlab platform.
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CSE/EUC/DCABES - Request-Size Aware Flash Translation Layer Based on Page-Level Mapping
2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th , 2016Co-Authors: Joon-young Paik, Taesun ChungAbstract:As more and more flash memory technologies quickly improve, NAND flash memory storage system has become more and more used as a non-volatile storage for embedded applications such as smart phones, smart watch, digital camera and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. However, the flash storage system does not perform well because of their Hardware Feature and the cost of garbage collection. To overcome this limitations, in this paper we provide a novel page mapping scheme named Request-Size aware Flash Translation Layer (RSaFTL) based on the page-level mapping algorithm. Our FTL is designed to reduce garbage collection overhead by using characteristics of overwriting one-page-unit data in flash memory. Experimental results show that RSaFTL outperforms the pure page mapping scheme by up to 29.4% on write-intensive workload with no addition RAM resource.
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CSE/EUC/DCABES - Request-Size Aware Flash Translation Layer Based on Page-Level Mapping
2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th , 2016Co-Authors: Joon-young Paik, Taesun ChungAbstract:As more and more flash memory technologies quickly improve, NAND flash memory storage system has become more and more used as a non-volatile storage for embedded applications such as smart phones, smart watch, digital camera and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. However, the flash storage system does not perform well because of their Hardware Feature and the cost of garbage collection. To overcome this limitations, in this paper we provide a novel page mapping scheme named Request-Size aware Flash Translation Layer (RSaFTL) based on the page-level mapping algorithm. Our FTL is designed to reduce garbage collection overhead by using characteristics of overwriting one-page-unit data in flash memory. Experimental results show that RSaFTL outperforms the pure page mapping scheme by up to 29.4% on write-intensive workload with no addition RAM resource.
Yehching Chung - One of the best experts on this subject based on the ideXlab platform.
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Hardware thread level speculation performance analysis
High Performance Computing and Communications, 2015Co-Authors: Yingchieh Wang, Cherung Lee, Ihsin Chung, Michael P Perrone, Yehching ChungAbstract:This paper presents performance analysis for Hardware Thread-Level Speculation (TLS) in the IBM Blue Gene/Q computer. Unlike traditional multi-thread programming model which uses lock to ensure the consistency of shared data, TLS is a harware mechanism to detect and resolve memory access conflicts among threads. The model shows good performance prediction, as verified by the experiments. This study helps to understand potential gains from using special purpose TLS Hardware to accelerate the performance of codes that, in a strict sense, require serial processing to avoid memory conflicts. Furthermore, based on analysis and measurements of the TLS behavior and its overhead together with OpenMP comparison, a strategy is proposed to help utilize this Hardware Feature. The results also suggest potential improvement for the future TLS architectural designs.
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HPCC/CSS/ICESS - Hardware Thread-Level Speculation Performance Analysis
2015 IEEE 17th International Conference on High Performance Computing and Communications 2015 IEEE 7th International Symposium on Cyberspace Safety an, 2015Co-Authors: Yingchieh Wang, Cherung Lee, Ihsin Chung, Michael P Perrone, Yehching ChungAbstract:This paper presents performance analysis for Hardware Thread-Level Speculation (TLS) in the IBM Blue Gene/Q computer. Unlike traditional multi-thread programming model which uses lock to ensure the consistency of shared data, TLS is a harware mechanism to detect and resolve memory access conflicts among threads. The model shows good performance prediction, as verified by the experiments. This study helps to understand potential gains from using special purpose TLS Hardware to accelerate the performance of codes that, in a strict sense, require serial processing to avoid memory conflicts. Furthermore, based on analysis and measurements of the TLS behavior and its overhead together with OpenMP comparison, a strategy is proposed to help utilize this Hardware Feature. The results also suggest potential improvement for the future TLS architectural designs.
