The Experts below are selected from a list of 41055 Experts worldwide ranked by ideXlab platform
Jason H Anderson - One of the best experts on this subject based on the ideXlab platform.
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range and bitmask analysis for Hardware Optimization in high level synthesis
Asia and South Pacific Design Automation Conference, 2013Co-Authors: Marcel Gort, Jason H AndersonAbstract:We consider the extent to which the bit-level representation of variables can be used to optimize Hardware generated by high-level synthesis (HLS). Two approaches to bit-level Optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to predetermine min/max ranges for variables to reduce the bitwidth required to represent variables in Hardware. Bitmask analysis characterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don't-cares permit Hardware to be eliminated under certain conditions. Static compiler-based analysis is contrasted with dynamic profiling-based analysis in terms of their potential to impact area and speed of HLS-generated Hardware. For a set of benchmarks implemented in the Altera Cyclone II FPGA, results show bit-level Optimizations in HLS based on static analysis reduce circuit area by 9%, on average, while additional Optimizations based on dynamic analysis provide 34% area reduction.
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ASP-DAC - Range and bitmask analysis for Hardware Optimization in high-level synthesis
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013Co-Authors: Marcel Gort, Jason H AndersonAbstract:We consider the extent to which the bit-level representation of variables can be used to optimize Hardware generated by high-level synthesis (HLS). Two approaches to bit-level Optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to predetermine min/max ranges for variables to reduce the bitwidth required to represent variables in Hardware. Bitmask analysis characterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don't-cares permit Hardware to be eliminated under certain conditions. Static compiler-based analysis is contrasted with dynamic profiling-based analysis in terms of their potential to impact area and speed of HLS-generated Hardware. For a set of benchmarks implemented in the Altera Cyclone II FPGA, results show bit-level Optimizations in HLS based on static analysis reduce circuit area by 9%, on average, while additional Optimizations based on dynamic analysis provide 34% area reduction.
Timothy G. Constandinou - One of the best experts on this subject based on the ideXlab platform.
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Adaptive spike detection and Hardware Optimization towards autonomous, high-channel-count BMIs.
Journal of neuroscience methods, 2021Co-Authors: Zheng Zhang, Timothy G. ConstandinouAbstract:Abstract Background The progress in microtechnology has enabled an exponential trend in the number of neurons that can be simultaneously recorded. The data bandwidth requirement is however increasing with channel count. The vast majority of experimental work involving electrophysiology stores the raw data and then processes this offline; to detect the underlying spike events. Emerging applications however require new methods for local, real-time processing. New Methods: We have developed an adaptive, low complexity spike detection algorithm that combines three novel components for: (1) removing the local field potentials; (2) enhancing the signal-to-noise ratio; and (3) computing an adaptive threshold. The proposed algorithm has been optimised for Hardware implementation (i.e. minimising computations, translating to a fixed-point implementation), and demonstrated on low-power embedded targets. Main results The algorithm has been validated on both synthetic datasets and real recordings yielding a detection sensitivity of up to 90%. The initial Hardware implementation using an off-the-shelf embedded platform demonstrated a memory requirement of less than 0.1 kb ROM and 3 kb program flash, consuming an average power of 130μW. Comparison with Existing Methods The method presented has the advantages over other approaches, that it allows spike events to be robustly detected in real-time from neural activity in a completely autonomous way, without the need for any calibration, and can be implemented with low Hardware resources. Conclusion The proposed method can detect spikes effectively and adaptively. It alleviates the need for re-calibration, which is critical towards achieving a viable BMI, and more so with future ‘high bandwidth’ systems’ targeting 1000s of channels.
Oreste Villa - One of the best experts on this subject based on the ideXlab platform.
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power performance Hardware Optimization for synchronization intensive applications in mpsocs
Design Automation and Test in Europe, 2006Co-Authors: Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste VillaAbstract:This paper explores Optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future power-efficient systems. The proposed solution is based on the idea of locally performing synchronization operations which require the continuous polling of a shared variable, thus featuring large contention (e. g. spin locks). We introduce a HW module, the Synchronization-operation Buffer (SB), which queues and manages the requests issued by the processors. Experimental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform. For 8-processor target architecture, we show that the proposed solution achieves up to 40% performance improvement and 30% energy saving with respect to synchronization based on directory-based coherence protocol.
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DATE - Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs
Proceedings of the Design Automation & Test in Europe Conference, 2006Co-Authors: Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste VillaAbstract:This paper explores Optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future power-efficient systems. The proposed solution is based on the idea of locally performing synchronization operations which require the continuous polling of a shared variable, thus featuring large contention (e. g. spin locks). We introduce a HW module, the Synchronization-operation Buffer (SB), which queues and manages the requests issued by the processors. Experimental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform. For 8-processor target architecture, we show that the proposed solution achieves up to 40% performance improvement and 30% energy saving with respect to synchronization based on directory-based coherence protocol.
Marcel Gort - One of the best experts on this subject based on the ideXlab platform.
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range and bitmask analysis for Hardware Optimization in high level synthesis
Asia and South Pacific Design Automation Conference, 2013Co-Authors: Marcel Gort, Jason H AndersonAbstract:We consider the extent to which the bit-level representation of variables can be used to optimize Hardware generated by high-level synthesis (HLS). Two approaches to bit-level Optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to predetermine min/max ranges for variables to reduce the bitwidth required to represent variables in Hardware. Bitmask analysis characterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don't-cares permit Hardware to be eliminated under certain conditions. Static compiler-based analysis is contrasted with dynamic profiling-based analysis in terms of their potential to impact area and speed of HLS-generated Hardware. For a set of benchmarks implemented in the Altera Cyclone II FPGA, results show bit-level Optimizations in HLS based on static analysis reduce circuit area by 9%, on average, while additional Optimizations based on dynamic analysis provide 34% area reduction.
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ASP-DAC - Range and bitmask analysis for Hardware Optimization in high-level synthesis
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013Co-Authors: Marcel Gort, Jason H AndersonAbstract:We consider the extent to which the bit-level representation of variables can be used to optimize Hardware generated by high-level synthesis (HLS). Two approaches to bit-level Optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to predetermine min/max ranges for variables to reduce the bitwidth required to represent variables in Hardware. Bitmask analysis characterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don't-cares permit Hardware to be eliminated under certain conditions. Static compiler-based analysis is contrasted with dynamic profiling-based analysis in terms of their potential to impact area and speed of HLS-generated Hardware. For a set of benchmarks implemented in the Altera Cyclone II FPGA, results show bit-level Optimizations in HLS based on static analysis reduce circuit area by 9%, on average, while additional Optimizations based on dynamic analysis provide 34% area reduction.
Antonio Teixeira - One of the best experts on this subject based on the ideXlab platform.
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Hardware Optimization for carrier recovery based on mth power schemes
Optical Fiber Communication Conference, 2016Co-Authors: Ricardo M Ferreira, Ali Shahpari, Fernando P Guiomar, Sofia B Amado, Miguel V Drummond, Jacklyn D Reis, Armando N Pinto, Antonio TeixeiraAbstract:We report a Hardware Optimization for frequency and phase recovery algorithms based on Mth-order power schemes, evaluating the accuracy of the reported architecture with an 8-bit DSP in real-time for a 1.25 and 2.5 Gb/s DQPSK signal.
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OFC - Hardware Optimization for carrier recovery based on Mth power schemes
Optical Fiber Communication Conference, 2016Co-Authors: Ricardo M Ferreira, Ali Shahpari, Fernando P Guiomar, Sofia B Amado, Miguel V Drummond, Jacklyn D Reis, Armando N Pinto, Antonio TeixeiraAbstract:We report a Hardware Optimization for frequency and phase recovery algorithms based on Mth-order power schemes, evaluating the accuracy of the reported architecture with an 8-bit DSP in real-time for a 1.25 and 2.5 Gb/s DQPSK signal.
