The Experts below are selected from a list of 69 Experts worldwide ranked by ideXlab platform
Tingting Hwang - One of the best experts on this subject based on the ideXlab platform.
-
Instruction buffering for nested loops in low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006Co-Authors: Chita Wu, Ang-chih Hsieh, Tingting HwangAbstract:Several loop-buffering techniques were proposed for reducing power consumption of embedded processors. Although the schemes are effective in reducing power, they work for unnested loops (or the inner-most loop in nested loops) only. In this paper, we propose a stack-based controller which can handle sequential loops being nested in a loop of all styles and the If-Then-Else Construct inside of a loop. Our experiments by power estimator Wattch show that the reduction in energy consumption using our technique is up to 36% improvement of the design without buffering technique and has 25% more improvement when compared to the results which handle inner-most loop only at the fetch and decode stages
-
Instruction buffering for nested loops in low power design
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002Co-Authors: Chita Wu, Tingting HwangAbstract:Loop buffering techniques have been proposed for reducing power consumption. Although such schemes are effective in reducing power, they work for the innermost loop only. In this paper, we propose a stack-based controller which can deal with nested-loops of all styles, and also the If-Then-Else Construct in a loop. Our experiments, using the Wattch power estimator (D. Brooks et al, Int. Symp. Comp. Architecture, pp. 83-94, 2000), show that the power consumption reduction of our technique at fetch and decode stages is up to 40% when compared to that of previously proposed techniques with the innermost loop only.
-
ISCAS (4) - Instruction buffering for nested loops in low power design
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002Co-Authors: Chita Wu, Tingting HwangAbstract:Loop buffering techniques have been proposed for reducing power consumption. Although such schemes are effective in reducing power, they work for the innermost loop only. In this paper, we propose a stack-based controller which can deal with nested-loops of all styles, and also the If-Then-Else Construct in a loop. Our experiments, using the Wattch power estimator (D. Brooks et al, Int. Symp. Comp. Architecture, pp. 83-94, 2000), show that the power consumption reduction of our technique at fetch and decode stages is up to 40% when compared to that of previously proposed techniques with the innermost loop only.
Chita Wu - One of the best experts on this subject based on the ideXlab platform.
-
Instruction buffering for nested loops in low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006Co-Authors: Chita Wu, Ang-chih Hsieh, Tingting HwangAbstract:Several loop-buffering techniques were proposed for reducing power consumption of embedded processors. Although the schemes are effective in reducing power, they work for unnested loops (or the inner-most loop in nested loops) only. In this paper, we propose a stack-based controller which can handle sequential loops being nested in a loop of all styles and the If-Then-Else Construct inside of a loop. Our experiments by power estimator Wattch show that the reduction in energy consumption using our technique is up to 36% improvement of the design without buffering technique and has 25% more improvement when compared to the results which handle inner-most loop only at the fetch and decode stages
-
Instruction buffering for nested loops in low power design
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002Co-Authors: Chita Wu, Tingting HwangAbstract:Loop buffering techniques have been proposed for reducing power consumption. Although such schemes are effective in reducing power, they work for the innermost loop only. In this paper, we propose a stack-based controller which can deal with nested-loops of all styles, and also the If-Then-Else Construct in a loop. Our experiments, using the Wattch power estimator (D. Brooks et al, Int. Symp. Comp. Architecture, pp. 83-94, 2000), show that the power consumption reduction of our technique at fetch and decode stages is up to 40% when compared to that of previously proposed techniques with the innermost loop only.
-
ISCAS (4) - Instruction buffering for nested loops in low power design
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002Co-Authors: Chita Wu, Tingting HwangAbstract:Loop buffering techniques have been proposed for reducing power consumption. Although such schemes are effective in reducing power, they work for the innermost loop only. In this paper, we propose a stack-based controller which can deal with nested-loops of all styles, and also the If-Then-Else Construct in a loop. Our experiments, using the Wattch power estimator (D. Brooks et al, Int. Symp. Comp. Architecture, pp. 83-94, 2000), show that the power consumption reduction of our technique at fetch and decode stages is up to 40% when compared to that of previously proposed techniques with the innermost loop only.
B. Calder - One of the best experts on this subject based on the ideXlab platform.
-
IEEE PACT - Dynamic hammock predication for non-predicated instruction set architectures
Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 1998Co-Authors: A. Klauser, T. Austin, D. Grunwald, B. CalderAbstract:Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However certain branches are difficult to predict. One solution to this problem is to evaluate both paths following such a conditional branch. Predicated execution can be used to implement this form of multi-path execution. Predicated architectures fetch and issue instructions that have associated predicates. These predicates indicate if the instruction should commit its result. Predicating a branch reduces the number of branches executed, eliminating the chance of branch misprediction at the cost of executing additional instructions. In this paper, we propose a restricted form of multi-path execution called Dynamic Predication for architectures with little or no support for predicated instructions in their instruction set. Dynamic predication dynamically predicates instruction sequences in the form of a branch hammock concurrently executing both paths of the branch. A branch hammock is a short forward branch that spans a few instructions in the form of an if-then or If-Then-Else Construct we mark these and other Constructs in the executable. When the decode stage detects such a sequence, it passes a predicated instruction sequence to a dynamically scheduled execution core. Our results show that dynamic predication can accrue speedups of up to 13%.
-
Dynamic hammock predication for non-predicated instruction set architectures
Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 1998Co-Authors: A. Klauser, T. Austin, D. Grunwald, B. CalderAbstract:Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However certain branches are difficult to predict. One solution to this problem is to evaluate both paths following such a conditional branch. Predicated execution can be used to implement this form of multi-path execution. Predicated architectures fetch and issue instructions that have associated predicates. These predicates indicate if the instruction should commit its result. Predicating a branch reduces the number of branches executed, eliminating the chance of branch misprediction at the cost of executing additional instructions. In this paper, we propose a restricted form of multi-path execution called Dynamic Predication for architectures with little or no support for predicated instructions in their instruction set. Dynamic predication dynamically predicates instruction sequences in the form of a branch hammock concurrently executing both paths of the branch. A branch hammock is a short forward branch that spans a few instructions in the form of an if-then or If-Then-Else Construct we mark these and other Constructs in the executable. When the decode stage detects such a sequence, it passes a predicated instruction sequence to a dynamically scheduled execution core. Our results show that dynamic predication can accrue speedups of up to 13%.
A. Klauser - One of the best experts on this subject based on the ideXlab platform.
-
IEEE PACT - Dynamic hammock predication for non-predicated instruction set architectures
Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 1998Co-Authors: A. Klauser, T. Austin, D. Grunwald, B. CalderAbstract:Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However certain branches are difficult to predict. One solution to this problem is to evaluate both paths following such a conditional branch. Predicated execution can be used to implement this form of multi-path execution. Predicated architectures fetch and issue instructions that have associated predicates. These predicates indicate if the instruction should commit its result. Predicating a branch reduces the number of branches executed, eliminating the chance of branch misprediction at the cost of executing additional instructions. In this paper, we propose a restricted form of multi-path execution called Dynamic Predication for architectures with little or no support for predicated instructions in their instruction set. Dynamic predication dynamically predicates instruction sequences in the form of a branch hammock concurrently executing both paths of the branch. A branch hammock is a short forward branch that spans a few instructions in the form of an if-then or If-Then-Else Construct we mark these and other Constructs in the executable. When the decode stage detects such a sequence, it passes a predicated instruction sequence to a dynamically scheduled execution core. Our results show that dynamic predication can accrue speedups of up to 13%.
-
Dynamic hammock predication for non-predicated instruction set architectures
Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 1998Co-Authors: A. Klauser, T. Austin, D. Grunwald, B. CalderAbstract:Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However certain branches are difficult to predict. One solution to this problem is to evaluate both paths following such a conditional branch. Predicated execution can be used to implement this form of multi-path execution. Predicated architectures fetch and issue instructions that have associated predicates. These predicates indicate if the instruction should commit its result. Predicating a branch reduces the number of branches executed, eliminating the chance of branch misprediction at the cost of executing additional instructions. In this paper, we propose a restricted form of multi-path execution called Dynamic Predication for architectures with little or no support for predicated instructions in their instruction set. Dynamic predication dynamically predicates instruction sequences in the form of a branch hammock concurrently executing both paths of the branch. A branch hammock is a short forward branch that spans a few instructions in the form of an if-then or If-Then-Else Construct we mark these and other Constructs in the executable. When the decode stage detects such a sequence, it passes a predicated instruction sequence to a dynamically scheduled execution core. Our results show that dynamic predication can accrue speedups of up to 13%.
D. Grunwald - One of the best experts on this subject based on the ideXlab platform.
-
IEEE PACT - Dynamic hammock predication for non-predicated instruction set architectures
Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 1998Co-Authors: A. Klauser, T. Austin, D. Grunwald, B. CalderAbstract:Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However certain branches are difficult to predict. One solution to this problem is to evaluate both paths following such a conditional branch. Predicated execution can be used to implement this form of multi-path execution. Predicated architectures fetch and issue instructions that have associated predicates. These predicates indicate if the instruction should commit its result. Predicating a branch reduces the number of branches executed, eliminating the chance of branch misprediction at the cost of executing additional instructions. In this paper, we propose a restricted form of multi-path execution called Dynamic Predication for architectures with little or no support for predicated instructions in their instruction set. Dynamic predication dynamically predicates instruction sequences in the form of a branch hammock concurrently executing both paths of the branch. A branch hammock is a short forward branch that spans a few instructions in the form of an if-then or If-Then-Else Construct we mark these and other Constructs in the executable. When the decode stage detects such a sequence, it passes a predicated instruction sequence to a dynamically scheduled execution core. Our results show that dynamic predication can accrue speedups of up to 13%.
-
Dynamic hammock predication for non-predicated instruction set architectures
Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 1998Co-Authors: A. Klauser, T. Austin, D. Grunwald, B. CalderAbstract:Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However certain branches are difficult to predict. One solution to this problem is to evaluate both paths following such a conditional branch. Predicated execution can be used to implement this form of multi-path execution. Predicated architectures fetch and issue instructions that have associated predicates. These predicates indicate if the instruction should commit its result. Predicating a branch reduces the number of branches executed, eliminating the chance of branch misprediction at the cost of executing additional instructions. In this paper, we propose a restricted form of multi-path execution called Dynamic Predication for architectures with little or no support for predicated instructions in their instruction set. Dynamic predication dynamically predicates instruction sequences in the form of a branch hammock concurrently executing both paths of the branch. A branch hammock is a short forward branch that spans a few instructions in the form of an if-then or If-Then-Else Construct we mark these and other Constructs in the executable. When the decode stage detects such a sequence, it passes a predicated instruction sequence to a dynamically scheduled execution core. Our results show that dynamic predication can accrue speedups of up to 13%.
