The Experts below are selected from a list of 476457 Experts worldwide ranked by ideXlab platform
Wancheng Zhang - One of the best experts on this subject based on the ideXlab platform.
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a 1 000 frames s programmable vision chip with variable resolution and row pixel mixed parallel Image Processors
Sensors, 2009Co-Authors: Qingyu Lin, Wei Miao, Wancheng ZhangAbstract:A programmable vision chip with variable resolution and row-pixel-mixed parallel Image Processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale Image Processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the Image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level Image processing and sends out features of the Image for various applications. It can perform Image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale Image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level Image processing and it can be applied in the real-time vision applications, such as high speed target tracking.
M Horino - One of the best experts on this subject based on the ideXlab platform.
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development of vehicle license number recognition system using real time Image processing and its application to travel time measurement
Vehicular Technology Conference, 1991Co-Authors: K Kanayama, Y Fujikawa, Koichi Fujimoto, M HorinoAbstract:In order to recognize vehicle license numbers in real time, a CCD (charge-coupled device) camera with electronic shutter and a hierarchical computer system with a general-purpose microprocessor and pipelined Image Processors have been developed. Much quicker extraction of the vehicle-license plate on the front-view Image is realized by optimization of parameters using Taguchi's method. Distinct Images outdoors can be obtained using a suitable control of the lens-diaphragm and continuous lighting via floodlight equipment. The results of field tests show that recognition rates of about 90% in the daytime and about 65% at night were attained. The processing time per vehicle is about 150 ms on average. >
Zhihua Wang - One of the best experts on this subject based on the ideXlab platform.
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7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2014Co-Authors: Cong Shi, Zhongxiang Cao, Qi Qin, Nan-jian Wu, Ye Han, Jie Yang, Liyuan Liu, Zhihua WangAbstract:A vision chip is a high-speed and compact vision system that integrates an Image sensor and parallel Image Processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array Processors to speed up low- and mid-level Image processing [1,2]. Recently, microProcessors (MPU) have been embedded to carry out high-level Image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the von Neumann bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from Image acquisition to high-level feature-recognition processing.
Kazuo Kyuma - One of the best experts on this subject based on the ideXlab platform.
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artificial retina chips as on chip Image Processors and gesture oriented interfaces
Optical Engineering, 1999Co-Authors: Hiroshi Kage, William T Freeman, Yasunari Miyake, Eiichi Funatsu, Kenichi Tanaka, Kazuo KyumaAbstract:Players of a video game may sometimes find the use of conventional interfaces inappropriate. In such cases, we think that interfaces realized with a vision-based gesture recognition system may find favor. The artificial retina (AR) chip is a versatile Image sensor whose use ranges from normal Image acquisition to on-chip Image processing, including on-chip Image convolution. In this paper, we describe a gesture- input video game system, with the AR module including the AR chip, and motion-based gesture recognition algorithms. We showed that the algorithms can be accelerated by projection data, the direct output from the AR chip. To show its performance, we have applied our system to two commercially available video games.
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artificial retinas fast versatile Image Processors
Nature, 1994Co-Authors: Kazuo Kyuma, Eberhard Lange, Jun Ohta, Anno Hermanns, Bryan Banish, Masaya OitaAbstract:Artificial retinas combine video camera and Image processing functions, allowing machines to function in their environment with unprecedented autonomy, or to augment quality control, surveillance and hazard monitoring. We review several retina devices and reveal how they execute basic manipulations of the Image at processing speeds well beyond the capabilities of the human eye.
Qingyu Lin - One of the best experts on this subject based on the ideXlab platform.
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a 1 000 frames s programmable vision chip with variable resolution and row pixel mixed parallel Image Processors
Sensors, 2009Co-Authors: Qingyu Lin, Wei Miao, Wancheng ZhangAbstract:A programmable vision chip with variable resolution and row-pixel-mixed parallel Image Processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale Image Processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the Image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level Image processing and sends out features of the Image for various applications. It can perform Image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale Image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level Image processing and it can be applied in the real-time vision applications, such as high speed target tracking.