The Experts below are selected from a list of 4884 Experts worldwide ranked by ideXlab platform
Isaac Keslassy - One of the best experts on this subject based on the ideXlab platform.
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on the code length of tcam coding schemes
International Symposium on Information Theory, 2010Co-Authors: Ori Rottenstreich, Isaac KeslassyAbstract:All high-speed Internet devices need to implement classification, i.e. they must determine whether Incoming Packet headers belong to a given subset of a search space. To do it, they encode the subset using ternary arrays in special high-speed devices called TCAMs (ternary content-addressable memories). However, the optimal coding for arbitrary subsets is unknown. In particular, to encode an arbitrary range subset of the space of all W-bit values, previous works have successively reduced the upper-bound on the code length from 2W–2 to 2W–4, then 2W–5, and finally W TCAM entries. In this paper, we prove that this final result is optimal for typical prefix coding and cannot be further improved, i.e. the bound of W is tight. To do so, we introduce new analytical tools based on independent sets and alternating paths.
Chuck Yoo - One of the best experts on this subject based on the ideXlab platform.
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Predictable Packet Latency in Xen-ARM
IEICE Transactions on Information and Systems, 2012Co-Authors: Seehwan Yoo, Kuen-hwan Kwak, Chuck YooAbstract:In this paper, we address latency issue in Xen-ARM virtual machines. Despite the advantages of virtualization in mobile systems, the current Xen-ARM is difficult to apply to mobile devices because it has unpredictable I/O latency. This paper analyzes the latency of Incoming Packet handling in Xen-ARM, and presents how virtualization affects the latency in detail. To make the latency predictable, firstly, we modify XenARM scheduler so that the driver domain can be promptly scheduled by the hypervisor. Secondly, we introduce additional paravirtualization of guest OS that minimizes non-preemptible code path. With our enhancements, 99% of Incoming Packets are predictably handled within one millisecond at the destined guest OS, which is a feasible time bound for most soft realtime applications. key words: virtual machine, I/O latency
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PAPER Predictable Packet Latency in Xen-ARM ∗
2012Co-Authors: Seehwan Yoo, Chuck YooAbstract:SUMMARY In this paper, we address latency issue in Xen-ARM virtual machines. Despite the advantages of virtualization in mobile systems, the current Xen-ARM is difficult to apply to mobile devices because it has unpredictable I/O latency. This paper analyzes the latency of Incoming Packet handling in Xen-ARM, and presents how virtualization affects the latency in detail. To make the latency predictable, firstly, we modify XenARM scheduler so that the driver domain can be promptly scheduled by the hypervisor. Secondly, we introduce additional paravirtualization of guest OS that minimizes non-preemptible code path. With our enhancements, 99% of Incoming Packets are predictably handled within one millisecond at the destined guest OS, which is a feasible time bound for most soft real
Hu Jin - One of the best experts on this subject based on the ideXlab platform.
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Minimum Cost Hypothesis Testing for Utility-Based Sleep-Mode
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018Co-Authors: Hu JinAbstract:This letter considers designing a utility-based sleep-mode for the system with a traffic source of Markov-modulated Poisson process. Our design framework makes use of the minimum cost hypothesis testing to detect the state of the traffic source. More specifically, observing a Packet arrival for a finite time interval, the system decides to enter sleep-mode with the hypothesis that the traffic source should be in the state with the lowest Packet arrival rate. In designing the hypothesis testing, we consider two sleep-modes, such as V-policy and N-policy, and show how long the system should observe an Incoming Packet and when to wake up under two sleep-modes in conjunction with discontinuous reception mechanism.This work was supported in part by DST under Grant no. RP03514G, and in part by the NRF grant funded by the Korea government (MSIT)(NRF-2017K1A3A1A19071179)
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Minimum Cost Hypothesis Testing for Utility-Based Sleep-Mode
IEEE Communications Letters, 2018Co-Authors: Jun-bae Seo, Hu JinAbstract:This letter considers designing a utility-based sleep-mode for the system with a traffic source of Markov-modulated Poisson process. Our design framework makes use of the minimum cost hypothesis testing to detect the state of the traffic source. More specifically, observing a Packet arrival for a finite time interval, the system decides to enter sleep-mode with the hypothesis that the traffic source should be in the state with the lowest Packet arrival rate. In designing the hypothesis testing, we consider two sleep-modes, such as $V$ -policy and $N$ -policy, and show how long the system should observe an Incoming Packet and when to wake up under two sleep-modes in conjunction with discontinuous reception mechanism.
V K Bhargava - One of the best experts on this subject based on the ideXlab platform.
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channel access delay and buffer distribution of two user opportunistic scheduling schemes in wireless networks
IEEE Transactions on Communications, 2010Co-Authors: Jahangir Hossain, Mohamedslim Alouini, V K BhargavaAbstract:In our earlier works, we proposed rate adaptive hierarchical modulation-assisted two-best user opportunistic scheduling (TBS) and hybrid two-user scheduling (HTS) schemes. The proposed schemes are innovative in the sense that they include a second user in the transmission opportunistically using hierarchical modulations. As such the frequency of information access of the users increases without any degradation of the system spectral efficiency (SSE) compared to the classical opportunistic scheduling scheme. In this paper, we analyze channel access delay of an Incoming Packet at the base station (BS) buffer when our proposed TBS and HTS schemes are employed at the BS. Specifically, using a queuing analytic model we derive channel access delay as well as buffer distribution of the Packets that wait at BS buffer for down-link (DL) transmission. We compare performance of the TBS and HTS schemes with that of the classical single user opportunistic schemes namely, absolute carrier-to-noise ratio (CNR)-based single user scheduling (ASS) and normalized CNR-based single user scheduling (NSS). For an independent and identically distributed (i.i.d.) fading environment, our proposed scheme can improve Packet's access delay performance compared to the ASS. Selected numerical results in an independent but non-identically distributed (i.n.d.) fading environment show that our proposed HTS achieves overall good channel access delay performance.
D Carver - One of the best experts on this subject based on the ideXlab platform.
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assisting network intrusion detection with reconfigurable hardware
Field-Programmable Custom Computing Machines, 2002Co-Authors: Brad Hutchings, R Franklin, D CarverAbstract:String matching is used by Network Intrusion Detection Systems (NIDS) to inspect Incoming Packet payloads for hostile data. String-matching speed is often the main factor limiting NIDS performance. String-matching performance can be dramatically improved by using Field-Programmable Gate Arrays (FPGAs); accordingly, a "regular-expression to FPGA circuit" module generator has been developed. The module generator extracts strings from the Snort NIDS rule-set, generates a regular expression that matches all extracted strings, synthesizes a FPGA-based string matching circuit, and generates an EDIF netlist that can be processed by Xilinx software to create an FPGA bitstream. The feasibility of this approach is demonstrated by comparing the performance of the FPGA-based string matcher against the software-based GNU regex program. The FPGA-based string matcher exceeds the performance of the software-based system by 600x for large patterns.
