The Experts below are selected from a list of 114 Experts worldwide ranked by ideXlab platform

David H. Albonesi - One of the best experts on this subject based on the ideXlab platform.

  • ReMAP: A Reconfigurable Architecture for Chip Multiprocessors
    IEEE Micro, 2011
    Co-Authors: Matthew A. Watkins, David H. Albonesi
    Abstract:

    ReMAP is a reconfigurable architecture for accelerating and parallelizing applications within a heterogeneous chip multiprocessor (CMP). Clusters of cores share a common reconfigurable fabric adaptable for Individual Thread computation or fine-grained communication with integrated computation. ReMAP demonstrates significantly higher performance and energy efficiency than hard-wired communication-only mechanisms, and over allocating the fabric area to additional or more powerful cores.

  • Enabling Parallelization via a Reconfigurable Chip Multiprocessor
    2010
    Co-Authors: Matthew A. Watkins, David H. Albonesi
    Abstract:

    While reconfigurable computing has traditionally involved attaching a reconfigurable fabric to a single processor core, the prospect of large-scale CMPs calls for a reevaluation of reconfigurable computing from the perspective of multicore architectures. We present ReMAPP, a reconfigurable architecture geared towards application acceleration and parallelization. In ReMAPP, parallel Threads share a common reconfigurable fabric which can be configured for Individual Thread computation or fine-grained communication with integrated computation. The architecture supports both fine-grained barrier synchronization and fine-grained point-to-point communication for pipeline parallelization. The combination of communication and configurable computation within ReMAPP provides the unique ability to perform customized computation while data is transferred between cores, and to execute custom global functions after barrier synchronization. We demonstrate that ReMAPP achieves significantly higher performance and energy efficiency compared to hard-wired communication- only mechanisms, and over what can ideally be achieved by allocating the fabric area to more cores.

  • MICRO - ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
    2010 43rd Annual IEEE ACM International Symposium on Microarchitecture, 2010
    Co-Authors: Matthew A. Watkins, David H. Albonesi
    Abstract:

    This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, Threads share a common reconfigurable fabric that can be configured for Individual Thread computation or fine-grained communication with integrated computation. The architecture supports both fine-grained point-to-point communication for pipeline parallelization and fine-grained barrier synchronization. The combination of communication and configurable computation within ReMAP provides the unique ability to perform customized computation while data is transferred between cores, and to execute custom global functions after barrier synchronization. ReMAP demonstrates significantly higher performance and energy efficiency compared to hard-wired communication-only mechanisms, and over what can ideally be achieved by allocating the fabric area to additional or more powerful cores.

Matthew A. Watkins - One of the best experts on this subject based on the ideXlab platform.

  • ReMAP: A Reconfigurable Architecture for Chip Multiprocessors
    IEEE Micro, 2011
    Co-Authors: Matthew A. Watkins, David H. Albonesi
    Abstract:

    ReMAP is a reconfigurable architecture for accelerating and parallelizing applications within a heterogeneous chip multiprocessor (CMP). Clusters of cores share a common reconfigurable fabric adaptable for Individual Thread computation or fine-grained communication with integrated computation. ReMAP demonstrates significantly higher performance and energy efficiency than hard-wired communication-only mechanisms, and over allocating the fabric area to additional or more powerful cores.

  • Enabling Parallelization via a Reconfigurable Chip Multiprocessor
    2010
    Co-Authors: Matthew A. Watkins, David H. Albonesi
    Abstract:

    While reconfigurable computing has traditionally involved attaching a reconfigurable fabric to a single processor core, the prospect of large-scale CMPs calls for a reevaluation of reconfigurable computing from the perspective of multicore architectures. We present ReMAPP, a reconfigurable architecture geared towards application acceleration and parallelization. In ReMAPP, parallel Threads share a common reconfigurable fabric which can be configured for Individual Thread computation or fine-grained communication with integrated computation. The architecture supports both fine-grained barrier synchronization and fine-grained point-to-point communication for pipeline parallelization. The combination of communication and configurable computation within ReMAPP provides the unique ability to perform customized computation while data is transferred between cores, and to execute custom global functions after barrier synchronization. We demonstrate that ReMAPP achieves significantly higher performance and energy efficiency compared to hard-wired communication- only mechanisms, and over what can ideally be achieved by allocating the fabric area to more cores.

  • MICRO - ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
    2010 43rd Annual IEEE ACM International Symposium on Microarchitecture, 2010
    Co-Authors: Matthew A. Watkins, David H. Albonesi
    Abstract:

    This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, Threads share a common reconfigurable fabric that can be configured for Individual Thread computation or fine-grained communication with integrated computation. The architecture supports both fine-grained point-to-point communication for pipeline parallelization and fine-grained barrier synchronization. The combination of communication and configurable computation within ReMAP provides the unique ability to perform customized computation while data is transferred between cores, and to execute custom global functions after barrier synchronization. ReMAP demonstrates significantly higher performance and energy efficiency compared to hard-wired communication-only mechanisms, and over what can ideally be achieved by allocating the fabric area to additional or more powerful cores.

Rajkishore Barik - One of the best experts on this subject based on the ideXlab platform.

  • May-Happen-in-Parallel Information for Concurrent Java Programs
    2007
    Co-Authors: Rajkishore Barik
    Abstract:

    Modeling of runtime Threads in static analysis of concur- rent programs plays an important role in both reducing the complexity and improving the precision of the analysis. Modeling based on type based techniques merges all runtime instances of a particular type and thereby introduces inaccuracy in the analysis. Other approaches model Individual runtime Threads explicitly in the analysis and are of high com- plexity. In this paper we introduce a Thread model that is both context and flow sensitive. Individual Thread abstractions are identified based on the context and multiplicity of the creation site. The interaction among these abstract Threads are depicted in a tree structure known as Thread Creation Tree (TCT). The TCT structure is subsequently exploited to efficiently compute May-Happen-in-Parallel (MHP) information for the analysis of multi-Threaded programs. For concurrent Java programs, our MHP computation algorithm runs 1.77x (on an average) faster than pre- viously reported MHP computation algorithm.

  • LCPC - Efficient computation of may-happen-in-parallel information for concurrent java programs
    Languages and Compilers for Parallel Computing, 2006
    Co-Authors: Rajkishore Barik
    Abstract:

    Modeling of runtime Threads in static analysis of concurrent programs plays an important role in both reducing the complexity and improving the precision of the analysis. Modeling based on type based techniques merges all runtime instances of a particular type and thereby introduces inaccuracy in the analysis. Other approaches model Individual runtime Threads explicitly in the analysis and are of high complexity. In this paper we introduce a Thread model that is both context and flow sensitive. Individual Thread abstractions are identified based on the context and multiplicity of the creation site. The interaction among these abstract Threads are depicted in a tree structure known as Thread Creation Tree (TCT). The TCT structure is subsequently exploited to efficiently compute May-Happen-in-Parallel (MHP) information for the analysis of multi-Threaded programs. For concurrent Java programs, our MHP computation algorithm runs 1.77x (on an average) faster than previously reported MHP computation algorithm.

  • Efficient computation of may-happen-in-parallel information for concurrent java programs
    Lecture Notes in Computer Science, 2006
    Co-Authors: Rajkishore Barik
    Abstract:

    Modeling of runtime Threads in static analysis of concurrent programs plays an important role in both reducing the complexity and improving the precision of the analysis. Modeling based on type based techniques merges all runtime instances of a particular type and thereby introduces inaccuracy in the analysis. Other approaches model Individual runtime Threads explicitly in the analysis and are of high complexity. In this paper we introduce a Thread model that is both context and flow sensitive. Individual Thread abstractions are identified based on the context and multiplicity of the creation site. The interaction among these abstract Threads are depicted in a tree structure known as Thread Creation Tree (TCT). The TCT structure is subsequently exploited to efficiently compute May-Happen-in-Parallel (MHP) information for the analysis of multi-Threaded programs. For concurrent Java programs, our MHP computation algorithm runs 1.77x (on an average) faster than previously reported MHP computation algorithm.

Toby Murray - One of the best experts on this subject based on the ideXlab platform.

  • FM - Value-Dependent Information-Flow Security on Weak Memory Models
    Lecture Notes in Computer Science, 2019
    Co-Authors: Graeme Smith, Nicholas Coughlin, Toby Murray
    Abstract:

    Weak memory models implemented on modern multicore processors are known to affect the correctness of concurrent code. They can also affect whether or not it is secure. This is particularly the case in programs where the security levels of variables are value-dependent, i.e., depend on the values of other variables. In this paper, we illustrate how instruction reordering allowed by contemporary multicore processors leads to vulnerabilities in such programs, and present a compositional, timing-sensitive information-flow logic which can be used to detect such vulnerabilities. The logic allows step-local reasoning (one instruction at a time) about a Thread’s security by tracking information about dependencies between instructions which guarantee their order of occurrence. Program security can then be established from Individual Thread security using rely/guarantee reasoning.

Manuel Prieto - One of the best experts on this subject based on the ideXlab platform.

  • ICPP - Improving Priority Enforcement via Non-Work-Conserving Scheduling
    2008 37th International Conference on Parallel Processing, 2008
    Co-Authors: Juan Carlos Saez, José Ignacio Gómez, Manuel Prieto
    Abstract:

    Current operating system schedulers are not fully aware of multi-core and multi-Threaded architectures, and as a result, schedule Threads in a way that may cause contention for critical resources such as the last level in the cache memory hierarchy or the memory access bandwidth. This contention has a significant impact on the system productivity and the quality of service that each Individual Thread gets from the platform, which can widely vary depending on the behavior of its simultaneous co-runners.In this paper we describe the design and implementation of a non-work-conserving framework to schedule Threads that tries to improve priority enforcement, based on on-line statistics collected through hardware performance counters. We have implemented our scheme in Linux running on both multicore and SMT processors. For synthetic workloads based on the latest SPEC CPU2006 benchmarks, our framework speeds up high-priority Threads by up to 50%, while keeping or even slightly improving the overall system throughput.