The Experts below are selected from a list of 57 Experts worldwide ranked by ideXlab platform

Artem Starostin - One of the best experts on this subject based on the ideXlab platform.

  • The original publication is available at www.springerlink.com Formal Pervasive Verification of a Paging Mechanism
    2015
    Co-Authors: Eyad Alkassar, Norbert Schirmer, Artem Starostin
    Abstract:

    Abstract. Memory virtualization by means of demand paging is a crucial com-ponent of every modern operating system. The formal verification is challenging since reasoning about the page fault handler has to cover two concurrent com-putational sources: the processor and the hard disk. We accurately model the in-terleaved executions of devices and the page fault handler, which is written in a high-level programming language with Inline Assembler portions. We describe how to combine results from sequential Hoare logic style reasoning about the page fault handler on the low-level concurrent machine model. To the best of our knowledge this is the first example of pervasive formal verification of software communicating with devices.

  • Formal pervasive verification of a paging mechanism
    2008
    Co-Authors: Eyad Alkassar, Norbert Schirmer, Artem Starostin
    Abstract:

    Abstract. Memory virtualization by means of demand paging is a crucial com-ponent of every modern operating system. The formal verification is challenging since reasoning about the page fault handler has to cover two concurrent com-putational sources: the processor and the hard disk. We accurately model the in-terleaved executions of devices and the page fault handler, which is written in a high-level programming language with Inline Assembler portions. We describe how to combine results from sequential Hoare logic style reasoning about the page fault handler on the low-level concurrent machine model. To the best of our knowledge this is the first example of pervasive formal verification of software communicating with devices.

  • Correct Microkernel Primitives
    Electronic Notes in Theoretical Computer Science, 2008
    Co-Authors: Artem Starostin, Alexandra Tsyban
    Abstract:

    Primitives are basic means provided by a microkernel to implementors of operating system services. Intensively used within every OS and commonly implemented in a mixture of high-level and assembly programming languages, primitives are meaningful and challenging candidates for formal verification. We report on the accomplished correctness proof of academic microkernel primitives. We describe how a novel approach to verification of programs written in C with Inline Assembler is successfully applied to a piece of realistic system software. Necessary and sufficient criteria covering functional correctness and requirements for the integration into a formal model of memory virtualization are determined and formally proven. The presented results are important milestones on the way to a pervasively verified operating system.

  • TACAS - Formal pervasive verification of a paging mechanism
    Tools and Algorithms for the Construction and Analysis of Systems, 1
    Co-Authors: Eyad Alkassar, Norbert Schirmer, Artem Starostin
    Abstract:

    Memory virtualization by means of demand paging is a crucial component of every modern operating system. The formal verification is challenging since reasoning about the page fault handler has to cover two concurrent computational sources: the processor and the hard disk. We accurately model the interleaved executions of devices and the page fault handler, which is written in a high-level programming language with Inline Assembler portions. We describe how to combine results from sequential Hoare logic style reasoning about the page fault handler on the low-level concurrent machine model. To the best of our knowledge this is the first example of pervasive formal verification of software communicating with devices.

Eyad Alkassar - One of the best experts on this subject based on the ideXlab platform.

  • The original publication is available at www.springerlink.com Formal Pervasive Verification of a Paging Mechanism
    2015
    Co-Authors: Eyad Alkassar, Norbert Schirmer, Artem Starostin
    Abstract:

    Abstract. Memory virtualization by means of demand paging is a crucial com-ponent of every modern operating system. The formal verification is challenging since reasoning about the page fault handler has to cover two concurrent com-putational sources: the processor and the hard disk. We accurately model the in-terleaved executions of devices and the page fault handler, which is written in a high-level programming language with Inline Assembler portions. We describe how to combine results from sequential Hoare logic style reasoning about the page fault handler on the low-level concurrent machine model. To the best of our knowledge this is the first example of pervasive formal verification of software communicating with devices.

  • Formal pervasive verification of a paging mechanism
    2008
    Co-Authors: Eyad Alkassar, Norbert Schirmer, Artem Starostin
    Abstract:

    Abstract. Memory virtualization by means of demand paging is a crucial com-ponent of every modern operating system. The formal verification is challenging since reasoning about the page fault handler has to cover two concurrent com-putational sources: the processor and the hard disk. We accurately model the in-terleaved executions of devices and the page fault handler, which is written in a high-level programming language with Inline Assembler portions. We describe how to combine results from sequential Hoare logic style reasoning about the page fault handler on the low-level concurrent machine model. To the best of our knowledge this is the first example of pervasive formal verification of software communicating with devices.

  • TACAS - Formal pervasive verification of a paging mechanism
    Tools and Algorithms for the Construction and Analysis of Systems, 1
    Co-Authors: Eyad Alkassar, Norbert Schirmer, Artem Starostin
    Abstract:

    Memory virtualization by means of demand paging is a crucial component of every modern operating system. The formal verification is challenging since reasoning about the page fault handler has to cover two concurrent computational sources: the processor and the hard disk. We accurately model the interleaved executions of devices and the page fault handler, which is written in a high-level programming language with Inline Assembler portions. We describe how to combine results from sequential Hoare logic style reasoning about the page fault handler on the low-level concurrent machine model. To the best of our knowledge this is the first example of pervasive formal verification of software communicating with devices.

Mathias Payer - One of the best experts on this subject based on the ideXlab platform.

  • LLDSAL: A Low-Level Domain-Specific Aspect Language for Dynamic Code-Generation and Program Modification
    2012
    Co-Authors: Mathias Payer, Boris Bluntschli, Thomas Gross
    Abstract:

    Dynamic binary translation frameworks enable late modifications of binary programs. The binary translator needs to generate dynamic code at runtime for trampolines, translated control flow instructions, additional runtime checks, and lookups. The code must be efficient, low-level, and cannot rely on any calling conventions. A Low-Level Domain Specific Aspect Language (LLD-SAL) is a natural fit to specify dynamically generated code snippets at compile time. The code is then generated by the translator on demand at runtime and integrated into the translated application code. The LLDSAL is tightly coupled to a host language and provides full access to data structures of the host language. The syntax of the LLDSAL is comparable to Inline Assembler but the code is generated at runtime. The advantage of an LLDSAL that generates dynamic code is that references to runtime data structures are encoded directly in the machine code without indirections. Most parameters in the generated low-level aspects can be hard coded to reduce the number of passed parameters. This paper presents the design and implementation of such an LLDSAL. The LLDSAL is integrated into a binary translation framework that enforces application security

  • DSAL@AOSD - LLDSAL: a low-level domain-specific aspect language for dynamic code-generation and program modification
    Proceedings of the seventh workshop on Domain-Specific Aspect Languages - DSAL '12, 2012
    Co-Authors: Mathias Payer, Boris Bluntschli, Thomas R. Gross
    Abstract:

    Dynamic binary translation frameworks enable late modifications of binary programs. The binary translator needs to generate dynamic code at runtime for trampolines, translated control flow instructions, additional runtime checks, and lookups. The code must be efficient, low-level, and cannot rely on any calling conventions. A Low-Level Domain Specific Aspect Language (LLDSAL) is a natural fit to specify dynamically generated code snippets at compile time. The code is then generated by the translator on demand at runtime and integrated into the translated application code. The LLDSAL is tightly coupled to a host language and provides full access to data structures of the host language. The syntax of the LLDSAL is comparable to Inline Assembler but the code is generated at runtime. The advantage of an LLDSAL that generates dynamic code is that references to runtime data structures are encoded directly in the machine code without indirections. Most parameters in the generated low-level aspects can be hard coded to reduce the number of passed parameters. This paper presents the design and implementation of such an LLDSAL. The LLDSAL is integrated into a binary translation framework that enforces application security.

Joseph Yiu - One of the best experts on this subject based on the ideXlab platform.

  • Assembly and Mixed Language Projects
    The Definitive Guide to ARM® CORTEX®-M3 and CORTEX®-M4 Processors, 2014
    Co-Authors: Joseph Yiu
    Abstract:

    This chapter looks into software development using assembly language and mixed language projects. Topics include how to create assembly language projects with the ARM ® tool chain (e.g., ARM DS-5™) and gcc, and various ways to mix assembly code and C code together using Inline Assembler, embedded Assembler, intrinsic functions.

  • Cortex-M3 Programming
    The Definitive Guide to the ARM Cortex-M3 TI, 2010
    Co-Authors: Joseph Yiu
    Abstract:

    This chapter discusses the programming in the Cortex-M3 processor. The Cortex-M3 can be programmed using either Assembler or C and because a lot of information on the way to do programming depends on the tool chain and silicon chips. C has the advantage of being portable and easier for implementing complex operations, compared to assembly language. Since it's a generic computer language, C does not specify how the processor is initialized. For these areas, tool chains can have different approaches. The best way to get started is to look at example codes. For users of ARM C compiler products such as RealView Development Suite (RVDS) or KEIL RealView Microcontroller Development Kit, a number of Cortex-M3 program examples are already included in the installation. Use of the C language can often speed up application development, but in many cases low-level system control still requires assembly code. Most ARM C compilers allow including assembly code, called Inline Assembler. This code is often necessary for many projects. For the Cortex-M3, Embedded Assembler is useful for tasks such as accessing special registers (MRS and MSR instructions; for example, setting up stack memory) or when it is necessary to use instructions that cannot be generated using C. When developing applications in C, it is recommended that one use the double word stack alignment function (configured by the STKALIGN bit in the NVIC Configuration Control register).

  • Chapter 10 – Cortex-M3 Programming
    The Definitive Guide to the ARM Cortex-M3, 2007
    Co-Authors: Joseph Yiu
    Abstract:

    Publisher Summary This chapter discusses the programming in the Cortex-M3 processor. The Cortex-M3 can be programmed using either Assembler or C and because a lot of information on the way to do programming depends on the tool chain and silicon chips. C has the advantage of being portable and easier for implementing complex operations, compared to assembly language. Since it's a generic computer language, C does not specify how the processor is initialized. For these areas, tool chains can have different approaches. The best way to get started is to look at example codes. For users of ARM C compiler products such as RealView Development Suite (RVDS) or KEIL RealView Microcontroller Development Kit, a number of Cortex-M3 program examples are already included in the installation. Use of the C language can often speed up application development, but in many cases low-level system control still requires assembly code. Most ARM C compilers allow including assembly code, called Inline Assembler. This code is often necessary for many projects. For the Cortex-M3, Embedded Assembler is useful for tasks such as accessing special registers (MRS and MSR instructions; for example, setting up stack memory) or when it is necessary to use instructions that cannot be generated using C. When developing applications in C, it is recommended that one use the double word stack alignment function (configured by the STKALIGN bit in the NVIC Configuration Control register).

Dragos Badea - One of the best experts on this subject based on the ideXlab platform.

  • model driven Inline Assembler generator for retargetable compilers
    International Conference on Control Systems and Computer Science, 2013
    Co-Authors: Ciprian Arbone, Bogdan Ditu, Stefan Craciun, Dragos Badea
    Abstract:

    This paper presents an automated method for implementing an Inline Assembler tool in a compiler, as opposed to manually writing such a software component. By using this approach, the retargetability time is considerably reduced and the maintenance process is improved. We are proposing a technique of automatically generating the Inline Assembler component of a compiler starting from a formal description of the target architecture. This is a single, consolidated model, shared among several tools and components that are part of the development chain. Such examples are: the Assembler, various compiler components (Inline Assembler, code generator and several code optimizing components), simulator, and debugger.

  • CSCS - Model-Driven Inline Assembler Generator for Retargetable Compilers
    2013 19th International Conference on Control Systems and Computer Science, 2013
    Co-Authors: Ciprian Arbone, Bogdan Ditu, Stefan Craciun, Dragos Badea
    Abstract:

    This paper presents an automated method for implementing an Inline Assembler tool in a compiler, as opposed to manually writing such a software component. By using this approach, the retargetability time is considerably reduced and the maintenance process is improved. We are proposing a technique of automatically generating the Inline Assembler component of a compiler starting from a formal description of the target architecture. This is a single, consolidated model, shared among several tools and components that are part of the development chain. Such examples are: the Assembler, various compiler components (Inline Assembler, code generator and several code optimizing components), simulator, and debugger.