The Experts below are selected from a list of 84 Experts worldwide ranked by ideXlab platform
Marios S Pattichis - One of the best experts on this subject based on the ideXlab platform.
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fast and scalable computation of the forward and inverse discrete periodic radon transform
IEEE Transactions on Image Processing, 2016Co-Authors: Cesar Carranza, Daniel Llamocca, Marios S PattichisAbstract:The discrete periodic radon transform (DPRT) has extensively been used in applications that involve image reconstructions from projections. Beyond classic applications, the DPRT can also be used to compute fast convolutions that avoids the use of floating-point arithmetic associated with the use of the fast Fourier transform. Unfortunately, the use of the DPRT has been limited by the need to compute a large number of additions and the need for a large number of memory accesses. This paper introduces a fast and scalable approach for computing the forward and inverse DPRT that is based on the use of: 1) a parallel array of fixed-point adder trees; 2) circular shift registers to remove the need for accessing external memory components when selecting the Input data for the adder trees; 3) an image block-based approach to DPRT computation that can fit the proposed architecture to available resources; and 4) fast transpositions that are computed in one or a few clock cycles that do not depend on the size of the Input image. As a result, for an $N\times N$ image ( $N$ prime), the proposed approach can compute up to $N^{2}$ additions per clock cycle. Compared with the previous approaches, the scalable approach provides the fastest known implementations for different amounts of computational resources. For example, for a $251\times 251$ image, for approximately 25% fewer flip-flops than required for a systolic implementation, we have that the scalable DPRT is computed 36 times faster. For the fastest case, we introduce optimized architectures that can compute the DPRT and its inverse in just $2N+\left \lceil{ \log _{2}N}\right \rceil +1$ and $2N+3\left \lceil{ \log _{2}N}\right \rceil +B+2$ cycles, respectively, where $B$ is the number of bits used to represent each Input Pixel. On the other hand, the scalable DPRT approach requires more 1-b additions than for the systolic implementation and provides a tradeoff between speed and additional 1-b additions. All of the proposed DPRT architectures were implemented in VHSIC Hardware Description Language (VHDL) and validated using an Field-Programmable Gate Array (FPGA) implementation.
Jan P. Allebach - One of the best experts on this subject based on the ideXlab platform.
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tone dependent error diffusion
IEEE Transactions on Image Processing, 2004Co-Authors: Pingshan Li, Jan P. AllebachAbstract:We present an enhanced error diffusion halftoning algorithm for which the filter weights and the quantizer thresholds vary depending on Input Pixel value. The weights and thresholds are optimized based on a human visual system model. Based on an analysis of the edge behavior, a tone dependent threshold is designed to reduce edge effects and start-up delay. We also propose an error diffusion system with parallel scan that uses variable weight locations to reduce worms.
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tone dependent error diffusion
electronic imaging, 2001Co-Authors: Pingshan Li, Jan P. AllebachAbstract:We present an enhanced error diffusion halftoning algorithm for which the filter weights and the quantizer thresholds vary depending on Input Pixel value. The weights and thresholds are optimized based on a human visual system model. Based on an analysis of the edge behavior, a tone dependent threshold is designed to reduce edge effects and start-up delay. We also propose an error diffusion system with parallel scan that uses variable weight locations to reduce worms.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Cesar Carranza - One of the best experts on this subject based on the ideXlab platform.
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fast and scalable computation of the forward and inverse discrete periodic radon transform
IEEE Transactions on Image Processing, 2016Co-Authors: Cesar Carranza, Daniel Llamocca, Marios S PattichisAbstract:The discrete periodic radon transform (DPRT) has extensively been used in applications that involve image reconstructions from projections. Beyond classic applications, the DPRT can also be used to compute fast convolutions that avoids the use of floating-point arithmetic associated with the use of the fast Fourier transform. Unfortunately, the use of the DPRT has been limited by the need to compute a large number of additions and the need for a large number of memory accesses. This paper introduces a fast and scalable approach for computing the forward and inverse DPRT that is based on the use of: 1) a parallel array of fixed-point adder trees; 2) circular shift registers to remove the need for accessing external memory components when selecting the Input data for the adder trees; 3) an image block-based approach to DPRT computation that can fit the proposed architecture to available resources; and 4) fast transpositions that are computed in one or a few clock cycles that do not depend on the size of the Input image. As a result, for an $N\times N$ image ( $N$ prime), the proposed approach can compute up to $N^{2}$ additions per clock cycle. Compared with the previous approaches, the scalable approach provides the fastest known implementations for different amounts of computational resources. For example, for a $251\times 251$ image, for approximately 25% fewer flip-flops than required for a systolic implementation, we have that the scalable DPRT is computed 36 times faster. For the fastest case, we introduce optimized architectures that can compute the DPRT and its inverse in just $2N+\left \lceil{ \log _{2}N}\right \rceil +1$ and $2N+3\left \lceil{ \log _{2}N}\right \rceil +B+2$ cycles, respectively, where $B$ is the number of bits used to represent each Input Pixel. On the other hand, the scalable DPRT approach requires more 1-b additions than for the systolic implementation and provides a tradeoff between speed and additional 1-b additions. All of the proposed DPRT architectures were implemented in VHSIC Hardware Description Language (VHDL) and validated using an Field-Programmable Gate Array (FPGA) implementation.
Pingshan Li - One of the best experts on this subject based on the ideXlab platform.
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tone dependent error diffusion
IEEE Transactions on Image Processing, 2004Co-Authors: Pingshan Li, Jan P. AllebachAbstract:We present an enhanced error diffusion halftoning algorithm for which the filter weights and the quantizer thresholds vary depending on Input Pixel value. The weights and thresholds are optimized based on a human visual system model. Based on an analysis of the edge behavior, a tone dependent threshold is designed to reduce edge effects and start-up delay. We also propose an error diffusion system with parallel scan that uses variable weight locations to reduce worms.
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tone dependent error diffusion
electronic imaging, 2001Co-Authors: Pingshan Li, Jan P. AllebachAbstract:We present an enhanced error diffusion halftoning algorithm for which the filter weights and the quantizer thresholds vary depending on Input Pixel value. The weights and thresholds are optimized based on a human visual system model. Based on an analysis of the edge behavior, a tone dependent threshold is designed to reduce edge effects and start-up delay. We also propose an error diffusion system with parallel scan that uses variable weight locations to reduce worms.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Daniel Llamocca - One of the best experts on this subject based on the ideXlab platform.
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fast and scalable computation of the forward and inverse discrete periodic radon transform
IEEE Transactions on Image Processing, 2016Co-Authors: Cesar Carranza, Daniel Llamocca, Marios S PattichisAbstract:The discrete periodic radon transform (DPRT) has extensively been used in applications that involve image reconstructions from projections. Beyond classic applications, the DPRT can also be used to compute fast convolutions that avoids the use of floating-point arithmetic associated with the use of the fast Fourier transform. Unfortunately, the use of the DPRT has been limited by the need to compute a large number of additions and the need for a large number of memory accesses. This paper introduces a fast and scalable approach for computing the forward and inverse DPRT that is based on the use of: 1) a parallel array of fixed-point adder trees; 2) circular shift registers to remove the need for accessing external memory components when selecting the Input data for the adder trees; 3) an image block-based approach to DPRT computation that can fit the proposed architecture to available resources; and 4) fast transpositions that are computed in one or a few clock cycles that do not depend on the size of the Input image. As a result, for an $N\times N$ image ( $N$ prime), the proposed approach can compute up to $N^{2}$ additions per clock cycle. Compared with the previous approaches, the scalable approach provides the fastest known implementations for different amounts of computational resources. For example, for a $251\times 251$ image, for approximately 25% fewer flip-flops than required for a systolic implementation, we have that the scalable DPRT is computed 36 times faster. For the fastest case, we introduce optimized architectures that can compute the DPRT and its inverse in just $2N+\left \lceil{ \log _{2}N}\right \rceil +1$ and $2N+3\left \lceil{ \log _{2}N}\right \rceil +B+2$ cycles, respectively, where $B$ is the number of bits used to represent each Input Pixel. On the other hand, the scalable DPRT approach requires more 1-b additions than for the systolic implementation and provides a tradeoff between speed and additional 1-b additions. All of the proposed DPRT architectures were implemented in VHSIC Hardware Description Language (VHDL) and validated using an Field-Programmable Gate Array (FPGA) implementation.