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Chulhee Kang - One of the best experts on this subject based on the ideXlab platform.

  • Input Register architectures of high speed router for supporting the phb of differentiated services
    International Workshop on Quality of Service, 2005
    Co-Authors: Sungkwan Youm, Seungjoon Seok, Seungjin Lee, Chulhee Kang
    Abstract:

    In this paper, we presents a new router architecture for supporting the Differentiated Services(DiffServ) in the Input-Registered router, which has multiple Virtual Output Registers(VORs) for buffering packets ahead of the non-blocking switching fabric. A queuing discipline function block needed on the DiffServ router is added in the Input-Registered router in order to support Per-Hop Behaviors(PHBs) of DiffServ. Also a new matching algorithm, First Scheduled First Matching (FSFM), is considered to match Input packets and output ports in the proposed VOR architecture. The simulation results by using ARENA show that the proposed architecture offer packet loss rate and delay close to the results of output-queued router with N time speed-up switch fabric in various PHBs on DiffServ.

  • QoS-IP - Input Register architectures of high speed router for supporting the PHB of differentiated services
    Quality of Service in Multiservice IP Networks, 2005
    Co-Authors: Sungkwan Youm, Seungjoon Seok, Seungjin Lee, Chulhee Kang
    Abstract:

    In this paper, we presents a new router architecture for supporting the Differentiated Services(DiffServ) in the Input-Registered router, which has multiple Virtual Output Registers(VORs) for buffering packets ahead of the non-blocking switching fabric. A queuing discipline function block needed on the DiffServ router is added in the Input-Registered router in order to support Per-Hop Behaviors(PHBs) of DiffServ. Also a new matching algorithm, First Scheduled First Matching (FSFM), is considered to match Input packets and output ports in the proposed VOR architecture. The simulation results by using ARENA show that the proposed architecture offer packet loss rate and delay close to the results of output-queued router with N time speed-up switch fabric in various PHBs on DiffServ.

Sungkwan Youm - One of the best experts on this subject based on the ideXlab platform.

  • Input Register architectures of high speed router for supporting the phb of differentiated services
    International Workshop on Quality of Service, 2005
    Co-Authors: Sungkwan Youm, Seungjoon Seok, Seungjin Lee, Chulhee Kang
    Abstract:

    In this paper, we presents a new router architecture for supporting the Differentiated Services(DiffServ) in the Input-Registered router, which has multiple Virtual Output Registers(VORs) for buffering packets ahead of the non-blocking switching fabric. A queuing discipline function block needed on the DiffServ router is added in the Input-Registered router in order to support Per-Hop Behaviors(PHBs) of DiffServ. Also a new matching algorithm, First Scheduled First Matching (FSFM), is considered to match Input packets and output ports in the proposed VOR architecture. The simulation results by using ARENA show that the proposed architecture offer packet loss rate and delay close to the results of output-queued router with N time speed-up switch fabric in various PHBs on DiffServ.

  • QoS-IP - Input Register architectures of high speed router for supporting the PHB of differentiated services
    Quality of Service in Multiservice IP Networks, 2005
    Co-Authors: Sungkwan Youm, Seungjoon Seok, Seungjin Lee, Chulhee Kang
    Abstract:

    In this paper, we presents a new router architecture for supporting the Differentiated Services(DiffServ) in the Input-Registered router, which has multiple Virtual Output Registers(VORs) for buffering packets ahead of the non-blocking switching fabric. A queuing discipline function block needed on the DiffServ router is added in the Input-Registered router in order to support Per-Hop Behaviors(PHBs) of DiffServ. Also a new matching algorithm, First Scheduled First Matching (FSFM), is considered to match Input packets and output ports in the proposed VOR architecture. The simulation results by using ARENA show that the proposed architecture offer packet loss rate and delay close to the results of output-queued router with N time speed-up switch fabric in various PHBs on DiffServ.

Seungjin Lee - One of the best experts on this subject based on the ideXlab platform.

  • Input Register architectures of high speed router for supporting the phb of differentiated services
    International Workshop on Quality of Service, 2005
    Co-Authors: Sungkwan Youm, Seungjoon Seok, Seungjin Lee, Chulhee Kang
    Abstract:

    In this paper, we presents a new router architecture for supporting the Differentiated Services(DiffServ) in the Input-Registered router, which has multiple Virtual Output Registers(VORs) for buffering packets ahead of the non-blocking switching fabric. A queuing discipline function block needed on the DiffServ router is added in the Input-Registered router in order to support Per-Hop Behaviors(PHBs) of DiffServ. Also a new matching algorithm, First Scheduled First Matching (FSFM), is considered to match Input packets and output ports in the proposed VOR architecture. The simulation results by using ARENA show that the proposed architecture offer packet loss rate and delay close to the results of output-queued router with N time speed-up switch fabric in various PHBs on DiffServ.

  • QoS-IP - Input Register architectures of high speed router for supporting the PHB of differentiated services
    Quality of Service in Multiservice IP Networks, 2005
    Co-Authors: Sungkwan Youm, Seungjoon Seok, Seungjin Lee, Chulhee Kang
    Abstract:

    In this paper, we presents a new router architecture for supporting the Differentiated Services(DiffServ) in the Input-Registered router, which has multiple Virtual Output Registers(VORs) for buffering packets ahead of the non-blocking switching fabric. A queuing discipline function block needed on the DiffServ router is added in the Input-Registered router in order to support Per-Hop Behaviors(PHBs) of DiffServ. Also a new matching algorithm, First Scheduled First Matching (FSFM), is considered to match Input packets and output ports in the proposed VOR architecture. The simulation results by using ARENA show that the proposed architecture offer packet loss rate and delay close to the results of output-queued router with N time speed-up switch fabric in various PHBs on DiffServ.

Seungjoon Seok - One of the best experts on this subject based on the ideXlab platform.

  • Input Register architectures of high speed router for supporting the phb of differentiated services
    International Workshop on Quality of Service, 2005
    Co-Authors: Sungkwan Youm, Seungjoon Seok, Seungjin Lee, Chulhee Kang
    Abstract:

    In this paper, we presents a new router architecture for supporting the Differentiated Services(DiffServ) in the Input-Registered router, which has multiple Virtual Output Registers(VORs) for buffering packets ahead of the non-blocking switching fabric. A queuing discipline function block needed on the DiffServ router is added in the Input-Registered router in order to support Per-Hop Behaviors(PHBs) of DiffServ. Also a new matching algorithm, First Scheduled First Matching (FSFM), is considered to match Input packets and output ports in the proposed VOR architecture. The simulation results by using ARENA show that the proposed architecture offer packet loss rate and delay close to the results of output-queued router with N time speed-up switch fabric in various PHBs on DiffServ.

  • QoS-IP - Input Register architectures of high speed router for supporting the PHB of differentiated services
    Quality of Service in Multiservice IP Networks, 2005
    Co-Authors: Sungkwan Youm, Seungjoon Seok, Seungjin Lee, Chulhee Kang
    Abstract:

    In this paper, we presents a new router architecture for supporting the Differentiated Services(DiffServ) in the Input-Registered router, which has multiple Virtual Output Registers(VORs) for buffering packets ahead of the non-blocking switching fabric. A queuing discipline function block needed on the DiffServ router is added in the Input-Registered router in order to support Per-Hop Behaviors(PHBs) of DiffServ. Also a new matching algorithm, First Scheduled First Matching (FSFM), is considered to match Input packets and output ports in the proposed VOR architecture. The simulation results by using ARENA show that the proposed architecture offer packet loss rate and delay close to the results of output-queued router with N time speed-up switch fabric in various PHBs on DiffServ.

P K Meher - One of the best experts on this subject based on the ideXlab platform.

  • IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 1 New Approach to Look-up-Table Design and Memory-Based Realization of FIR Digital Filter
    2016
    Co-Authors: P K Meher, Senior Member
    Abstract:

    Abstract—Distributed arithmetic (DA)-based computation is popular for its potential for efficient memory-based implementa-tion of finite impulse response (FIR) filter where the filter outputs are computed as inner-product of Input-sample vectors and filter-coefficient vector. In this paper, however, we show that the look-up-table (LUT)-multiplier-based approach, where the memory elements store all the possible values of products of the filter coefficients could be an area-efficient alternative to DA-based design of FIR filter with the same throughput of implementation. By operand and inner-product decompositions, respectively, we have designed the conventional LUT-multiplier-based and DA-based structures for FIR filter of equivalent throughput, where the LUT-multiplier-based design involves nearly the same mem-ory and the same number of adders, and less number of Input Register at the cost of slightly higher adder-widths than the other. Moreover, we present two new approaches to LUT-based multiplication, which could be used to reduce the memory size to half of the conventional LUT-based multiplication. Besides, we present a modified transposed form FIR filter, where a single segmented memory-core with only one pair of decoders are used to minimize the combinational area. The proposed LUT-based FIR filter is found to involve nearly half the memory-space and (1/N) times the complexity of decoders and Input-Registers, at the cost of marginal increase in the width of the adders, and additional ∼ (4N×W) AND-OR-INVERT gates and ∼ (2N×W) NOR gates. We have synthesized the DA-based design and LUT-multiplier based design of 16-tap FIR filters by Synopsys Design Compiler using TSMC 90 nm library, and find that the proposed LUT-multiplier-based design involves nearly 15 % less area than the DA-based design for the same throughput and lower latency of implementation. Index Terms—Memory-based computing, distributed arith-metic, FIR filter, LUT-based computing, digital signal processing (DSP) chip, VLSI. I

  • new approach to look up table design and memory based realization of fir digital filter
    IEEE Transactions on Circuits and Systems I-regular Papers, 2010
    Co-Authors: P K Meher
    Abstract:

    Distributed arithmetic (DA)-based computation is popular for its potential for efficient memory-based implementation of finite impulse response (FIR) filter where the filter outputs are computed as inner-product of Input-sample vectors and filter-coefficient vector. In this paper, however, we show that the look-up-table (LUT)-multiplier-based approach, where the memory elements store all the possible values of products of the filter coefficients could be an area-efficient alternative to DA-based design of FIR filter with the same throughput of implementation. By operand and inner-product decompositions, respectively, we have designed the conventional LUT-multiplier-based and DA-based structures for FIR filter of equivalent throughput, where the LUT-multiplier-based design involves nearly the same memory and the same number of adders, and less number of Input Register at the cost of slightly higher adder-widths than the other. Moreover, we present two new approaches to LUT-based multiplication, which could be used to reduce the memory size to half of the conventional LUT-based multiplication. Besides, we present a modified transposed form FIR filter, where a single segmented memory-core with only one pair of decoders are used to minimize the combinational area. The proposed LUT-based FIR filter is found to involve nearly half the memory-space and $(1/N)$ times the complexity of decoders and Input-Registers, at the cost of marginal increase in the width of the adders, and additional $\sim(4N\times W)$ AND-OR-INVERT gates and $\sim(2N\times W)$ NOR gates. We have synthesized the DA-based design and LUT-multiplier based design of 16-tap FIR filters by Synopsys Design Compiler using TSMC 90 nm library, and find that the proposed LUT-multiplier-based design involves nearly 15% less area than the DA-based design for the same throughput and lower latency of implementation.