The Experts below are selected from a list of 2889 Experts worldwide ranked by ideXlab platform
Yale N Patt - One of the best experts on this subject based on the ideXlab platform.
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author retrospective for increasing the Instruction Fetch rate via multiple branch prediction and a branch address cache
International Conference on Supercomputing, 2014Co-Authors: Tseyu Yeh, Deborah T Marr, Yale N PattAbstract:"Increasing the Instruction Fetch Rate viaMultiple Branch Prediction and a Branch Address Cache" was the first paper to propose a highly accurate hardware mechanism for predicting and Fetching multiple non-contiguous basic blocks using leading-edge aggressive branch predictors of the time. Prior to this paper, the methods to increase Fetch bandwidth relied on software and compiler mechanisms to increase the size of the basic blocks themselves. The publication of our paper inspired an explosion of research to further improve the accuracy of multiple branch prediction, reduce complexity of Fetching multiple basic blocks, or increase the Fetch bandwidth in other ways. Our HPS research group defied conventional wisdom in a 1991 ISCA paper [1] that demonstrated Instruction level parallelism (IPC) can be greater than two even for non-scientific workloads. This flew in the face of numerous "proofs" at the time. We showed that there was enough parallelism for an aggressive superscalar out-of-order execution engine to exploit to dramatically improve performance, provided that the penalties caused by incorrect branch predictions, cache misses, and TLB misses could be improved.
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ICS 25th Anniversary - Author retrospective for increasing the Instruction Fetch rate via multiple branch prediction and a branch address cache
25th Anniversary International Conference on Supercomputing Anniversary Volume -, 2014Co-Authors: Tseyu Yeh, Deborah T Marr, Yale N PattAbstract:"Increasing the Instruction Fetch Rate viaMultiple Branch Prediction and a Branch Address Cache" was the first paper to propose a highly accurate hardware mechanism for predicting and Fetching multiple non-contiguous basic blocks using leading-edge aggressive branch predictors of the time. Prior to this paper, the methods to increase Fetch bandwidth relied on software and compiler mechanisms to increase the size of the basic blocks themselves. The publication of our paper inspired an explosion of research to further improve the accuracy of multiple branch prediction, reduce complexity of Fetching multiple basic blocks, or increase the Fetch bandwidth in other ways. Our HPS research group defied conventional wisdom in a 1991 ISCA paper [1] that demonstrated Instruction level parallelism (IPC) can be greater than two even for non-scientific workloads. This flew in the face of numerous "proofs" at the time. We showed that there was enough parallelism for an aggressive superscalar out-of-order execution engine to exploit to dramatically improve performance, provided that the penalties caused by incorrect branch predictions, cache misses, and TLB misses could be improved.
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Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures
International Journal of Parallel Programming, 1998Co-Authors: Po-yung Chang, Marius Evers, Yale N PattAbstract:To exploit larger amounts of Instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction Fetch rate must also be increased in order to effectively exploit the performance potential of such processors. Block-structured ISAs provide an effective means of increasing the Instruction Fetch rate. We define an optimization, called block enlargement, that can be applied to a block-structured ISA to increase the Instruction Fetch rate of a processor that implements that ISA. We have constructed a compiler that generates block-structured ISA code, and a simulator that models the execution of that code on a block-structured ISA processor. We show that for the SPECint95 benchmarks, the block-structured ISA improves the performance of an aggressive wide issue, dynamically scheduled processor by 15% while using simpler microarchitectural mechanisms to support wide issue and dynamic scheduling.
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MICRO - Increasing the Instruction Fetch rate via block-structured Instruction set architectures
International Journal of Parallel Programming, 1998Co-Authors: Eric Hao, Marius Evers, Po-yung Chang, Yale N PattAbstract:To exploit larger amounts of Instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction Fetch rate must also be increased in order to effectively exploit the performance potential of such processors. Block-structured ISAs provide an effective means of increasing the Instruction Fetch rare. We define an optimization, called block enlargement, that can be applied to a block-structured ISA to increase the Instruction Fetch rate of a processor that implements that ISA. We have constructed a compiler that generates block-structured ISA code, and a simulator that models the execution of that code on a block-structured ISA processor. We show that for the SPECint95 benchmarks, the block-structured ISA processor executing enlarged atomic blocks outperforms a conventional ISA processor by 12% while using simpler microarchitectural mechanisms to support wide-issue and dynamic scheduling.
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increasing the Instruction Fetch rate via block structured Instruction set architectures
International Symposium on Microarchitecture, 1996Co-Authors: Eric Hao, Marius Evers, Po-yung Chang, Yale N PattAbstract:To exploit larger amounts of Instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction Fetch rate must also be increased in order to effectively exploit the performance potential of such processors. Block-structured ISAs provide an effective means of increasing the Instruction Fetch rare. We define an optimization, called block enlargement, that can be applied to a block-structured ISA to increase the Instruction Fetch rate of a processor that implements that ISA. We have constructed a compiler that generates block-structured ISA code, and a simulator that models the execution of that code on a block-structured ISA processor. We show that for the SPECint95 benchmarks, the block-structured ISA processor executing enlarged atomic blocks outperforms a conventional ISA processor by 12% while using simpler microarchitectural mechanisms to support wide-issue and dynamic scheduling.
Kenji Kise - One of the best experts on this subject based on the ideXlab platform.
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an efficient Instruction Fetch architecture for a risc v soft processor on an fpga
Heart, 2019Co-Authors: Hiromu Miyazaki, Junya Miura, Kenji KiseAbstract:To reduce the code size of application programs for RISC-V soft processors on an FPGA, it is desirable for the processor to support the RISC-V compressed Instruction extension. In this paper, we implement an efficient Instruction Fetch unit. We clarify the problem of Instruction Fetching in pipelining processors that support the extension. To solve the problem of Instruction Fetching, we propose two Instruction Fetch units using a decompressed cache and a compressed cache, respectively. We implement the proposed Fetch units and evaluate their performance, hardware resources, and operating frequency. Through the evaluation, we show that the proposed unit with a compressed cache is the best and achieves 21.8% better Fetch performance using reasonable hardware resources than the baseline architecture.
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HEART - An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA
Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies - HEART 2019, 2019Co-Authors: Hiromu Miyazaki, Junya Miura, Kenji KiseAbstract:To reduce the code size of application programs for RISC-V soft processors on an FPGA, it is desirable for the processor to support the RISC-V compressed Instruction extension. In this paper, we implement an efficient Instruction Fetch unit. We clarify the problem of Instruction Fetching in pipelining processors that support the extension. To solve the problem of Instruction Fetching, we propose two Instruction Fetch units using a decompressed cache and a compressed cache, respectively. We implement the proposed Fetch units and evaluate their performance, hardware resources, and operating frequency. Through the evaluation, we show that the proposed unit with a compressed cache is the best and achieves 21.8% better Fetch performance using reasonable hardware resources than the baseline architecture.
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ISOCC - Rethinking processor Instruction Fetch: Inefficiencies-cracking mechanism
2011 International SoC Design Conference, 2011Co-Authors: Mochamad Asri, Naoki Fujieda, Kenji KiseAbstract:Identification of inefficiencies in some parts of conventional processor mechanism and its countermeasure are required in order to tackle conflicting design requirement in embedded system processors design. In this paper, we proposed a novel architecture which combines large entry of Instruction Register along with unique binary translation to aim more efficient Fetch mechanism that leads to further reduction of processor's code size. From simulation result, we found that the proposed method succeeded in reducing code size significantly compared to conventional processor.
Babak Falsafi - One of the best experts on this subject based on the ideXlab platform.
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shift shared history Instruction Fetch for lean core server processors
International Symposium on Microarchitecture, 2013Co-Authors: Cansu Kaynak, Boris Grot, Babak FalsafiAbstract:In server workloads, large Instruction working sets result in high L1 Instruction cache miss rates. Fast access requirements preclude large Instruction caches that can accommodate the deep software stacks prevalent in server applications. PreFetching has been a promising approach to mitigate Instruction-Fetch stalls by relying on recurring Instruction streams of server workloads to predict future Instruction misses. By recording and replaying Instruction streams from dedicated storage next to each core, stream-based preFetchers have been shown to overcome Instruction Fetch stalls. Problematically, existing stream-based preFetchers incur high history storage costs resulting from large Instruction working sets and complex control flow inherent in server workloads. The high storage requirements of these preFetchers prohibit their use in emerging lean-core server processors. We introduce Shared History Instruction Fetch, SHIFT, an Instruction preFetcher suitable for lean-core server processors. By sharing the history across cores, SHIFT minimizes the cost per core without sacrificing miss coverage. Moreover, by embedding the shared Instruction history in the LLC, SHIFT obviates the need for dedicated Instruction history storage, while transparently enabling multiple Instruction histories in the presence of workload consolidation. In a 16-core server CMP, SHIFT eliminates 81% (up to 93%) of Instruction cache misses, achieving 19% (up to 42%) speedup on average. SHIFT captures 90% of the performance benefit of the state-of-the-art Instruction preFetcher at 14x less storage cost.
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MICRO - SHIFT: shared history Instruction Fetch for lean-core server processors
Proceedings of the 46th Annual IEEE ACM International Symposium on Microarchitecture - MICRO-46, 2013Co-Authors: Cansu Kaynak, Boris Grot, Babak FalsafiAbstract:In server workloads, large Instruction working sets result in high L1 Instruction cache miss rates. Fast access requirements preclude large Instruction caches that can accommodate the deep software stacks prevalent in server applications. PreFetching has been a promising approach to mitigate Instruction-Fetch stalls by relying on recurring Instruction streams of server workloads to predict future Instruction misses. By recording and replaying Instruction streams from dedicated storage next to each core, stream-based preFetchers have been shown to overcome Instruction Fetch stalls. Problematically, existing stream-based preFetchers incur high history storage costs resulting from large Instruction working sets and complex control flow inherent in server workloads. The high storage requirements of these preFetchers prohibit their use in emerging lean-core server processors. We introduce Shared History Instruction Fetch, SHIFT, an Instruction preFetcher suitable for lean-core server processors. By sharing the history across cores, SHIFT minimizes the cost per core without sacrificing miss coverage. Moreover, by embedding the shared Instruction history in the LLC, SHIFT obviates the need for dedicated Instruction history storage, while transparently enabling multiple Instruction histories in the presence of workload consolidation. In a 16-core server CMP, SHIFT eliminates 81% (up to 93%) of Instruction cache misses, achieving 19% (up to 42%) speedup on average. SHIFT captures 90% of the performance benefit of the state-of-the-art Instruction preFetcher at 14x less storage cost.
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proactive Instruction Fetch
International Symposium on Microarchitecture, 2011Co-Authors: Michael Ferdman, Cansu Kaynak, Babak FalsafiAbstract:Fast access requirements preclude building L1 Instruction caches large enough to capture the working set of server workloads. Efforts exist to mitigate limited L1 Instruction cache capacity by relying on the stability and repetitiveness of the Instruction stream to predict and preFetch future Instruction blocks prior to their use. However, dynamic variation in cache miss sequences prevents correct and timely prediction, leaving many Instruction-Fetch stalls exposed, resulting in a key performance bottleneck for servers. We observe that, while the vast majority of application Instruction references are amenable to prediction, even minor control-flow variations are amplified by microarchitectural components, resulting in a major source of instability and randomness that significantly limit preFetcher utility. Control-flow variation disturbs the L1 Instruction cache replacement order and branch predictor state, causing the L1 Instruction cache to randomly filter the Instruction stream while the branch predictor and spontaneous hardware interrupts inject the stream with unpredictable noise. Based on this observation, we show that an Instruction preFetcher, previously plagued by microarchitectural instability, becomes nearly perfect when modified to operate on the correct-path, retire-order Instruction stream. We propose Proactive Instruction Fetch, an Instruction preFetch mechanism that achieves higher than 99.5% Instruction-cache hit rate, improving server throughput by 27% and nearly matching the performance of a perfect L1 Instruction cache that never misses.
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MICRO - Proactive Instruction Fetch
Proceedings of the 44th Annual IEEE ACM International Symposium on Microarchitecture - MICRO-44 '11, 2011Co-Authors: Michael Ferdman, Cansu Kaynak, Babak FalsafiAbstract:Fast access requirements preclude building L1 Instruction caches large enough to capture the working set of server workloads. Efforts exist to mitigate limited L1 Instruction cache capacity by relying on the stability and repetitiveness of the Instruction stream to predict and preFetch future Instruction blocks prior to their use. However, dynamic variation in cache miss sequences prevents correct and timely prediction, leaving many Instruction-Fetch stalls exposed, resulting in a key performance bottleneck for servers. We observe that, while the vast majority of application Instruction references are amenable to prediction, even minor control-flow variations are amplified by microarchitectural components, resulting in a major source of instability and randomness that significantly limit preFetcher utility. Control-flow variation disturbs the L1 Instruction cache replacement order and branch predictor state, causing the L1 Instruction cache to randomly filter the Instruction stream while the branch predictor and spontaneous hardware interrupts inject the stream with unpredictable noise. Based on this observation, we show that an Instruction preFetcher, previously plagued by microarchitectural instability, becomes nearly perfect when modified to operate on the correct-path, retire-order Instruction stream. We propose Proactive Instruction Fetch, an Instruction preFetch mechanism that achieves higher than 99.5% Instruction-cache hit rate, improving server throughput by 27% and nearly matching the performance of a perfect L1 Instruction cache that never misses.
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temporal Instruction Fetch streaming
International Symposium on Microarchitecture, 2008Co-Authors: Michael Ferdman, Babak Falsafi, Thomas F Wenisch, Anastasia Ailamaki, Andreas MoshovosAbstract:L1 Instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 Instruction caches large enough to capture the application, library, and OS Instruction working sets of these workloads. To cope with capacity constraints, researchers have proposed Instruction preFetchers that use branch predictors to explore future control flow. However, such preFetchers suffer from several fundamental flaws: their lookahead is limited by branch prediction bandwidth, their accuracy suffers from geometrically-compounding branch misprediction probability, and they are ignorant of the cache contents, frequently predicting blocks already present in L1. Hence, L1 Instruction misses remain a bottleneck. We propose temporal Instruction Fetch streaming (TIFS)-a mechanism for preFetching temporally-correlated Instruction streams from lower-level caches. Rather than explore a programpsilas control flow graph, TIFS predicts future Instruction-cache misses directly, through recording and replaying recurring L1 Instruction miss sequences. In this paper, we first present an information-theoretic offline trace analysis of Instruction-miss repetition to show that 94% of L1 Instruction misses occur in long, recurring sequences. Then, we describe a practical mechanism to record these recurring sequences in the L2 cache and leverage them for Instruction-cache preFetching. Our TIFS design requires less than 5% storage overhead over the baseline L2 cache and improves performance by 11% on average and 24% at best in a suite of commercial server workloads.
Tseyu Yeh - One of the best experts on this subject based on the ideXlab platform.
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author retrospective for increasing the Instruction Fetch rate via multiple branch prediction and a branch address cache
International Conference on Supercomputing, 2014Co-Authors: Tseyu Yeh, Deborah T Marr, Yale N PattAbstract:"Increasing the Instruction Fetch Rate viaMultiple Branch Prediction and a Branch Address Cache" was the first paper to propose a highly accurate hardware mechanism for predicting and Fetching multiple non-contiguous basic blocks using leading-edge aggressive branch predictors of the time. Prior to this paper, the methods to increase Fetch bandwidth relied on software and compiler mechanisms to increase the size of the basic blocks themselves. The publication of our paper inspired an explosion of research to further improve the accuracy of multiple branch prediction, reduce complexity of Fetching multiple basic blocks, or increase the Fetch bandwidth in other ways. Our HPS research group defied conventional wisdom in a 1991 ISCA paper [1] that demonstrated Instruction level parallelism (IPC) can be greater than two even for non-scientific workloads. This flew in the face of numerous "proofs" at the time. We showed that there was enough parallelism for an aggressive superscalar out-of-order execution engine to exploit to dramatically improve performance, provided that the penalties caused by incorrect branch predictions, cache misses, and TLB misses could be improved.
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ICS 25th Anniversary - Author retrospective for increasing the Instruction Fetch rate via multiple branch prediction and a branch address cache
25th Anniversary International Conference on Supercomputing Anniversary Volume -, 2014Co-Authors: Tseyu Yeh, Deborah T Marr, Yale N PattAbstract:"Increasing the Instruction Fetch Rate viaMultiple Branch Prediction and a Branch Address Cache" was the first paper to propose a highly accurate hardware mechanism for predicting and Fetching multiple non-contiguous basic blocks using leading-edge aggressive branch predictors of the time. Prior to this paper, the methods to increase Fetch bandwidth relied on software and compiler mechanisms to increase the size of the basic blocks themselves. The publication of our paper inspired an explosion of research to further improve the accuracy of multiple branch prediction, reduce complexity of Fetching multiple basic blocks, or increase the Fetch bandwidth in other ways. Our HPS research group defied conventional wisdom in a 1991 ISCA paper [1] that demonstrated Instruction level parallelism (IPC) can be greater than two even for non-scientific workloads. This flew in the face of numerous "proofs" at the time. We showed that there was enough parallelism for an aggressive superscalar out-of-order execution engine to exploit to dramatically improve performance, provided that the penalties caused by incorrect branch predictions, cache misses, and TLB misses could be improved.
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Two-level adaptive branch prediction and Instruction Fetch mechanisms for high performance superscalar processors
1993Co-Authors: Tseyu YehAbstract:As the issue width and depth of pipelining of high performance superscalar processors increase, the importance of an effective Instruction Fetch mechanism becomes vital to delivering the potential performance of a wide-issue, deep pipelined microarchitecture. In this thesis a new dynamic branch predictor (Two-Level Adaptive Branch Prediction) and a new Instruction Fetch mechanism suitable for superscalar processors are proposed to reduce the branch execution penalty in Instruction Fetch. The branch predictor uses two levels of branch history information to make predictions: the history of the last k branches encountered, and the branch behavior for the last s occurrences of the specific pattern of these k branches. Its nine variations are identified according to how finely the history information is gathered. The cost-effectiveness of the variations is compared. Simulation results show that the average misprediction rate for the Two-Level Adaptive branch predictor with a reasonable implementation cost is 3% over nine programs in the SPEC89 benchmark suite, while other known schemes achieve at least 5.6% average misprediction rate. The branch predictor is integrated into an Instruction Fetch mechanism that is able to Fetch multiple Instructions each cycle and change Instruction flow without incurring any pipeline bubbles. Compared with designs which use other branch predictors, the proposed design significantly reduces the branch execution penalty.
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a comprehensive Instruction Fetch mechanism for a processor supporting speculative execution
International Symposium on Microarchitecture, 1992Co-Authors: Tseyu Yeh, Yale N PattAbstract:A superscalar processor supporting speculative execution requires an Instruction Fetch mechanism that can provide Instruction Fetch addresses as nearly correct as possible and as soon as possible in order to reduce the likelihood of throwing away speculative work. In this paper we propose a comprehensive Instruction Fetch mechanism to satisfy that need. Implementation issues are identified, possible solutions and designs for resolving those issues are simulated, and the results of these simulations are presented. A metric for measuring the average penalty of executing a branch Instruction is introduced and used to evaluate the performance of our Instruction Fetch mechanism. We achieve an average performance of 1.19 IPC on the original SPEC benchmarks in a machine which can execute five Instructions ideally by using the proposed mechanism.
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MICRO - A comprehensive Instruction Fetch mechanism for a processor supporting speculative execution
ACM SIGMICRO Newsletter, 1992Co-Authors: Tseyu Yeh, Yale N PattAbstract:A superscalar processor supporting speculative execution requires an Instruction Fetch mechanism that can provide Instruction Fetch addresses as nearly correct as possible and as soon as possible in order to reduce the likelihood of throwing away speculative work. In this paper we propose a comprehensive Instruction Fetch mechanism to satisfy that need. Implementation issues are identified, possible solutions and designs for resolving those issues are simulated, and the results of these simulations are presented. A metric for measuring the average penalty of executing a branch Instruction is introduced and used to evaluate the performance of our Instruction Fetch mechanism. We achieve an average performance of 1.19 IPC on the original SPEC benchmarks in a machine which can execute five Instructions ideally by using the proposed mechanism.
Thomas M Conte - One of the best experts on this subject based on the ideXlab platform.
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Instruction Fetch mechanisms for vliw architectures with compressed encodings
International Symposium on Microarchitecture, 1996Co-Authors: Thomas M Conte, Sanjeev Banerjia, Sergei Y Larin, Kishore N Menezes, Sumedh W SathayeAbstract:VLIW architectures use very wide Instruction words in conjunction with high bandwidth to the Instruction cache to achieve multiple Instruction issue. This report uses the TINKER experimental testbed to examine Instruction Fetch and Instruction cache mechanisms for VLIWs. A compressed Instruction encoding for VLIWs is defined and a classification scheme for i-Fetch hardware for such an encoding is introduced. Several interesting cache and i-Fetch organizations are described and evaluated through trace-driven simulations. A new i-Fetch mechanism using a silo cache is found to have the best performance.
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optimization of Instruction Fetch mechanisms for high issue rates
International Symposium on Computer Architecture, 1995Co-Authors: Thomas M Conte, Kishore N Menezes, Patrick Mills, Burzin A PatelAbstract:Recent superscalar processors issue four Instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be exploited when fed by high Instruction bandwidth. This task is the responsibility of the Instruction Fetch unit. Accurate branch prediction and low I-cache miss ratios are essential for the efficient operation of the Fetch unit. Several studies on cache design and branch prediction address this problem. However, these techniques are not sufficient. Even in the presence of efficient cache designs and branch prediction, the Fetch unit must continuously extract multiple, non-sequential Instructions from the Instruction cache, realign these in the proper order, and supply them to the decoder. This paper explores solutions to this problem and presents several schemes with varying degrees of performance and cost. The most-general scheme, the collapsing buffer, achieves near-perfect performance and consistently aligns Instructions in excess of 90% of the time, over a wide range of issue rates. The performance boost provided by compiler optimization techniques is also investigated. Results show that compiler optimization can significantly enhance performance across all schemes. The collapsing buffer supplemented by compiler techniques remains the best-performing mechanism. The paper closes with recommendations and suggestions for future.
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ISCA - Optimization of Instruction Fetch mechanisms for high issue rates
Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95, 1995Co-Authors: Thomas M Conte, Kishore N Menezes, Patrick Mills, Burzin A PatelAbstract:Recent superscalar processors issue four Instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be exploited when fed by high Instruction bandwidth. This task is the responsibility of the Instruction Fetch unit. Accurate branch prediction and low I-cache miss ratios are essential for the efficient operation of the Fetch unit. Several studies on cache design and branch prediction address this problem. However, these techniques are not sufficient. Even in the presence of efficient cache designs and branch prediction, the Fetch unit must continuously extract multiple, non-sequential Instructions from the Instruction cache, realign these in the proper order, and supply them to the decoder. This paper explores solutions to this problem and presents several schemes with varying degrees of performance and cost. The most-general scheme, the collapsing buffer, achieves near-perfect performance and consistently aligns Instructions in excess of 90% of the time, over a wide range of issue rates. The performance boost provided by compiler optimization techniques is also investigated. Results show that compiler optimization can significantly enhance performance across all schemes. The collapsing buffer supplemented by compiler techniques remains the best-performing mechanism. The paper closes with recommendations and suggestions for future.
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MICRO - Instruction Fetch mechanisms for VLIW architectures with compressed encodings
Proceedings of the 29th Annual IEEE ACM International Symposium on Microarchitecture. MICRO 29, 1Co-Authors: Thomas M Conte, Sanjeev Banerjia, Sergei Y Larin, Kishore N Menezes, Sumedh W SathayeAbstract:VLIW architectures use very wide Instruction words in conjunction with high bandwidth to the Instruction cache to achieve multiple Instruction issue. This report uses the TINKER experimental testbed to examine Instruction Fetch and Instruction cache mechanisms for VLIWs. A compressed Instruction encoding for VLIWs is defined and a classification scheme for i-Fetch hardware for such an encoding is introduced. Several interesting cache and i-Fetch organizations are described and evaluated through trace-driven simulations. A new i-Fetch mechanism using a silo cache is found to have the best performance.
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Computer design strategy for MCM-D/flip-chip technology
Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit, 1Co-Authors: Paul D. Franzon, Thomas M Conte, A. Glaser, S. Lipa, S. Banerjia, T. Schaffer, S. Alvorez, A. Stanaski, Y. TekmenAbstract:A compelling case is made for using MCM-D (thin film MultiChip Module) flip-chip technology to build a 'MegaChip' CPU consisting of an Instruction Fetch Unit and Execution Unit. By building part of the Instruction Fetch Unit in an optimized SRAM process, significant performance/cost gains are made. We also address the following important 'implementation' (1) Partitioning high speed paths across the chip boundary within timing specs; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; (4) Managing test costs; and (5) implementing a debug strategy. This paradigm is also potentially useful for other memory intensive applications, including ATM, etc.