The Experts below are selected from a list of 162 Experts worldwide ranked by ideXlab platform
Joerg Henkel - One of the best experts on this subject based on the ideXlab platform.
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Instruction Trace compression for rapid Instruction cache simulation
Design Automation and Test in Europe, 2007Co-Authors: Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg HenkelAbstract:Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular application. To find the best cache size suited for a particular embedded system, the application(s) is/are executed, Traces obtained, and caches simulated. Typically, program Trace files can range from a few megabytes to several gigabytes. Simulation of cache performance using large program Trace files is a time consuming process. In this paper, a novel Instruction cache simulation methodology that can operate directly on a compressed program Trace file without the need for decompression is presented. This feature allowed our simulation methodology to have an average speed up of 9.67 times compared to the existing state of the art tool (Dinero IV cache simulator), for a range of applications from the Mediabench suite.
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DATE - Instruction Trace compression for rapid Instruction cache simulation
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg HenkelAbstract:Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular application. To find the best cache size suited for a particular embedded system, the applications) is/are executed, Traces obtained, and caches simulated. Typically, program Trace files can range from a few megabytes to several gigabytes. Simulation of cache performance using large program Trace files is a time consuming process. In this paper, a novel Instruction cache simulation methodology that can operate directly on a compressed program Trace file without the need for decompression is presented. This feature allowed our simulation methodology to have an average speed up of 9.67 times compared to the existing state of the art tool (Dinero IV cache simulator), for a range of applications from the Mediabench suite. © 2007 EDAA
Andhi Janapsatya - One of the best experts on this subject based on the ideXlab platform.
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Instruction Trace compression for rapid Instruction cache simulation
Design Automation and Test in Europe, 2007Co-Authors: Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg HenkelAbstract:Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular application. To find the best cache size suited for a particular embedded system, the application(s) is/are executed, Traces obtained, and caches simulated. Typically, program Trace files can range from a few megabytes to several gigabytes. Simulation of cache performance using large program Trace files is a time consuming process. In this paper, a novel Instruction cache simulation methodology that can operate directly on a compressed program Trace file without the need for decompression is presented. This feature allowed our simulation methodology to have an average speed up of 9.67 times compared to the existing state of the art tool (Dinero IV cache simulator), for a range of applications from the Mediabench suite.
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DATE - Instruction Trace compression for rapid Instruction cache simulation
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg HenkelAbstract:Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular application. To find the best cache size suited for a particular embedded system, the applications) is/are executed, Traces obtained, and caches simulated. Typically, program Trace files can range from a few megabytes to several gigabytes. Simulation of cache performance using large program Trace files is a time consuming process. In this paper, a novel Instruction cache simulation methodology that can operate directly on a compressed program Trace file without the need for decompression is presented. This feature allowed our simulation methodology to have an average speed up of 9.67 times compared to the existing state of the art tool (Dinero IV cache simulator), for a range of applications from the Mediabench suite. © 2007 EDAA
Sri Parameswaran - One of the best experts on this subject based on the ideXlab platform.
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Instruction Trace compression for rapid Instruction cache simulation
Design Automation and Test in Europe, 2007Co-Authors: Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg HenkelAbstract:Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular application. To find the best cache size suited for a particular embedded system, the application(s) is/are executed, Traces obtained, and caches simulated. Typically, program Trace files can range from a few megabytes to several gigabytes. Simulation of cache performance using large program Trace files is a time consuming process. In this paper, a novel Instruction cache simulation methodology that can operate directly on a compressed program Trace file without the need for decompression is presented. This feature allowed our simulation methodology to have an average speed up of 9.67 times compared to the existing state of the art tool (Dinero IV cache simulator), for a range of applications from the Mediabench suite.
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DATE - Instruction Trace compression for rapid Instruction cache simulation
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg HenkelAbstract:Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular application. To find the best cache size suited for a particular embedded system, the applications) is/are executed, Traces obtained, and caches simulated. Typically, program Trace files can range from a few megabytes to several gigabytes. Simulation of cache performance using large program Trace files is a time consuming process. In this paper, a novel Instruction cache simulation methodology that can operate directly on a compressed program Trace file without the need for decompression is presented. This feature allowed our simulation methodology to have an average speed up of 9.67 times compared to the existing state of the art tool (Dinero IV cache simulator), for a range of applications from the Mediabench suite. © 2007 EDAA
Aleksandar Ignjatovic - One of the best experts on this subject based on the ideXlab platform.
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Instruction Trace compression for rapid Instruction cache simulation
Design Automation and Test in Europe, 2007Co-Authors: Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg HenkelAbstract:Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular application. To find the best cache size suited for a particular embedded system, the application(s) is/are executed, Traces obtained, and caches simulated. Typically, program Trace files can range from a few megabytes to several gigabytes. Simulation of cache performance using large program Trace files is a time consuming process. In this paper, a novel Instruction cache simulation methodology that can operate directly on a compressed program Trace file without the need for decompression is presented. This feature allowed our simulation methodology to have an average speed up of 9.67 times compared to the existing state of the art tool (Dinero IV cache simulator), for a range of applications from the Mediabench suite.
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DATE - Instruction Trace compression for rapid Instruction cache simulation
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg HenkelAbstract:Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular application. To find the best cache size suited for a particular embedded system, the applications) is/are executed, Traces obtained, and caches simulated. Typically, program Trace files can range from a few megabytes to several gigabytes. Simulation of cache performance using large program Trace files is a time consuming process. In this paper, a novel Instruction cache simulation methodology that can operate directly on a compressed program Trace file without the need for decompression is presented. This feature allowed our simulation methodology to have an average speed up of 9.67 times compared to the existing state of the art tool (Dinero IV cache simulator), for a range of applications from the Mediabench suite. © 2007 EDAA
Jamese . Smith - One of the best experts on this subject based on the ideXlab platform.
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25 Years ISCA: Retrospectives and Reprints - A study of branch prediction strategies
25 years of the international symposia on Computer architecture (selected papers) - ISCA '98, 1998Co-Authors: Jamese . SmithAbstract:In high-performance computer systems, performance losses due to conditional branch Instructions can be minimized by predicting a branch outcome and fetching, decoding, and/or issuing subsequent Instructions before the actual outcome is known. This paper discusses branch prediction strategies with the goal of maximizing prediction accuracy. First, currently used techniques are discussed and analyzed using Instruction Trace data. Then, new techniques are proposed and are shown to provide greater accuracy and more flexibility at low cost.
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IEEE PACT - Modeling Superscalar Processors via Statistical Simulation
Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques, 1Co-Authors: Sébastien Nussbaum, Jamese . SmithAbstract:Abstract: Statistical simulation is a technique for fast performance evaluation of superscalar processors. First, intrinsic statistical information is collected from a single detailed simulation of a program. This information is then used to generate a synthetic Instruction Trace that is fed to a simple processor model, along with cache and branch prediction statistics. Because of the probabilistic nature of the simulation, it quickly converges to a performance rate. The simplicity and simulation speed make it useful for fast design space exploration; as such, it is a good complement to conventional detailed simulation. The accuracy of this technique is evaluated for different levels of modeling complexity. Both errors and convergence properties are studied in detail. A simple Instruction model yields an average error of 8% compared with detailed simulation. A more detailed Instruction model reduces the error to 5% but requires about three times as long to converge.
