The Experts below are selected from a list of 30 Experts worldwide ranked by ideXlab platform

Ricardo Reis - One of the best experts on this subject based on the ideXlab platform.

  • 3d Integrated Circuit Layout visualization using vrml
    Future Generation Computer Systems, 2001
    Co-Authors: Leandro Soares Indrusiak, Ricardo Reis
    Abstract:

    Abstract This paper introduces the virtual reality modeling language (VRML) as a way to describe the Layout of Integrated Circuits. Using this language, the Circuit can be viewed in three dimensions, adding the depth dimension, not present in the regular Layout description languages. A conversion tool that parses 2D Circuit Layout descriptions and converts it into 3D VRML models is presented. A discussion about other applications of VRML on Integrated Circuits design and on educational tools is also included.

Leandro Soares Indrusiak - One of the best experts on this subject based on the ideXlab platform.

  • 3d Integrated Circuit Layout visualization using vrml
    Future Generation Computer Systems, 2001
    Co-Authors: Leandro Soares Indrusiak, Ricardo Reis
    Abstract:

    Abstract This paper introduces the virtual reality modeling language (VRML) as a way to describe the Layout of Integrated Circuits. Using this language, the Circuit can be viewed in three dimensions, adding the depth dimension, not present in the regular Layout description languages. A conversion tool that parses 2D Circuit Layout descriptions and converts it into 3D VRML models is presented. A discussion about other applications of VRML on Integrated Circuits design and on educational tools is also included.

Avideh Zakhor - One of the best experts on this subject based on the ideXlab platform.

  • Lossless compression of VLSI Layout image data
    IEEE Transactions on Image Processing, 2006
    Co-Authors: Avideh Zakhor
    Abstract:

    We present a novel lossless compression algorithm called Context Copy Combinatorial Code (C4), which integrates the advantages of two very disparate compression techniques: context-based modeling and Lempel-Ziv (LZ) style copying. While the algorithm can be applied to many lossless compression applications, such as document image compression, our primary target application has been lossless compression of Integrated Circuit Layout image data. These images contain a heterogeneous mix of data: dense repetitive data better suited to LZ-style coding, and less dense structured data, better suited to context-based encoding. As part of C4, we have developed a novel binary entropy coding technique called combinatorial coding which is simultaneously as efficient as arithmetic coding, and as fast as Huffman coding. Compression results show C4 outperforms JBIG, ZIP, BZIP2, and two-dimensional LZ, and achieves lossless compression ratios greater than 22 for binary Layout image data, and greater than 14 for gray-pixel image data

H Samueli - One of the best experts on this subject based on the ideXlab platform.

  • design techniques for silicon compiler implementations of high speed fir digital filters
    IEEE Journal of Solid-state Circuits, 1996
    Co-Authors: R Hawley, C Wong, J Laskowski, H Samueli
    Abstract:

    Architecture design techniques for implementing both single-rate and multirate high throughput finite impulse response (FIR) digital filters are explored, with an emphasis on those which are applicable to automated Integrated Circuit Layout techniques. Various parallel architectures are examined based on the criteria of achievable throughput versus hardware complexity. Well-known techniques for reduced complexity and computation time are briefly summarized, followed by the introduction of several new techniques which offer further gains in both throughput and Circuitry reduction. An architecture for mirror-symmetric polyphase filter banks is derived which exploits the coefficient symmetry between multiple filters to reduce hardware. Finally, the evolution of a silicon compiler which utilizes all of these techniques is presented, and results are given for compiled filters along with comparisons to other compiled and custom FIR filter chips.

Aguilar Loreto Oma - One of the best experts on this subject based on the ideXlab platform.

  • ANÁLISIS DEL ALGORITMO DE CORRIMIENTO DE FASE DE CUATRO PASOS PARA IMPLEMENTACIONES VLSI (FOUR-STEP PHASE SHIFT ALGORITHM ANALYSIS FOR VLSI IMPLEMENTATIONS)
    Tecnológico Nacional de México en Celaya, 2019
    Co-Authors: Flores Centeno, Jorge Alfonso, Gurrola Navarro, Marco Antonio, Muñoz Gómez, José Antonio, Chávez Bracamontes Ramó, Aguilar Loreto Oma
    Abstract:

    Resumen   En este artículo se realiza un análisis del algoritmo de corrimiento de fase de cuatro pasos para su implementación en Circuito integrado digital. Como resultado de este análisis, estaremos en posibilidades de implementar un microprocesador de aplicación específica optimizado para ejecutar el algoritmo mencionado. Este tipo de algoritmos encuentran su campo de aplicación en reconstrucción tridimensional de objetos mediante la proyección de patrones de franjas corridos en fase. La idea es que siguiendo el procedimiento de análisis aquí presentado al final conoceremos cual es la cantidad mínima de registros que debe contener el procesador y la longitud mínima en bits para representar los datos sin perder precisión en el resultado final. Así mismo, conoceremos las operaciones que la unidad aritmético lógica debe ser capaz de realizar y la cantidad de memoria RAM externa necesaria en nuestro sistema. Este tipo de análisis es un paso previo y necesario a la descripción del procesador mediante un lenguaje de descripción de hardware y la elaboración del plano del Circuito integrado con la ayuda de herramientas de síntesis digital. Palabras Clave: algoritmo CORDIC, fase envuelta, síntesis VLSI, reconstrucción 3D. Abstract  This article analyzes the four-step phase shift algorithm for its implementation in a digital Integrated Circuit. As a result we will be able to implement a specific application microprocessor optimized to execute the aforementioned algorithm. These types of algorithms find their field of application in 3D surface reconstruction by fringe projections techniques. The idea is that following the analysis procedure presented here at the end we will know what is the minimum number of records that the processor must contain and the minimum length in bits is to represent the data without losing precision in the final result. Likewise, we will know the operations that the logical arithmetic unit must be able to perform, and the amount of external RAM needed in our system. This type of analysis is a previous and necessary step to the description of the processor through a hardware description language and the elaboration of the Integrated Circuit Layout with the help of digital synthesis tools.Keywords: 3D-reconstruction, CORDIC algorithm, VLSI synthesis, wrapped phase