The Experts below are selected from a list of 48417 Experts worldwide ranked by ideXlab platform
J. Becker - One of the best experts on this subject based on the ideXlab platform.
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ISVLSI - Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-ReConfiguration of Spartan 3 FPGAs
2008 IEEE Computer Society Annual Symposium on VLSI, 2008Co-Authors: K. Paulsson, M. Hubner, Ulrich Viereck, J. BeckerAbstract:Field programmable gate arrays, FPGAs, are increasingly often applied in various industrial applications as well as investigated in different research projects. Due to the possibility for performing parallel computations, this kind of hardware architecture is especially interesting for high-performance applications. Dynamic and partial hardware reConfiguration, which is provided by several FPGA families such as the Xilinx Spartan 3 and Virtex 2/4 families, further increases the flexibility of these architectures. The Spartan 3 family was a less attractive choice for performing dynamic and partial reConfiguration due to the lack of an Internal Configuration port. However, a virtual Internal Configuration port, JCAP, has previously been realized by using the external JTAG interface. This paper presents an approach for Internal Configuration readback for failure detection and task migration by extending the JCAP core functionality. The paper also presents the first results from implementing self-reConfiguration over JCAP.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
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FPL - Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
K. Paulsson - One of the best experts on this subject based on the ideXlab platform.
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ISVLSI - Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-ReConfiguration of Spartan 3 FPGAs
2008 IEEE Computer Society Annual Symposium on VLSI, 2008Co-Authors: K. Paulsson, M. Hubner, Ulrich Viereck, J. BeckerAbstract:Field programmable gate arrays, FPGAs, are increasingly often applied in various industrial applications as well as investigated in different research projects. Due to the possibility for performing parallel computations, this kind of hardware architecture is especially interesting for high-performance applications. Dynamic and partial hardware reConfiguration, which is provided by several FPGA families such as the Xilinx Spartan 3 and Virtex 2/4 families, further increases the flexibility of these architectures. The Spartan 3 family was a less attractive choice for performing dynamic and partial reConfiguration due to the lack of an Internal Configuration port. However, a virtual Internal Configuration port, JCAP, has previously been realized by using the external JTAG interface. This paper presents an approach for Internal Configuration readback for failure detection and task migration by extending the JCAP core functionality. The paper also presents the first results from implementing self-reConfiguration over JCAP.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
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FPL - Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
M. Hubner - One of the best experts on this subject based on the ideXlab platform.
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ISVLSI - Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-ReConfiguration of Spartan 3 FPGAs
2008 IEEE Computer Society Annual Symposium on VLSI, 2008Co-Authors: K. Paulsson, M. Hubner, Ulrich Viereck, J. BeckerAbstract:Field programmable gate arrays, FPGAs, are increasingly often applied in various industrial applications as well as investigated in different research projects. Due to the possibility for performing parallel computations, this kind of hardware architecture is especially interesting for high-performance applications. Dynamic and partial hardware reConfiguration, which is provided by several FPGA families such as the Xilinx Spartan 3 and Virtex 2/4 families, further increases the flexibility of these architectures. The Spartan 3 family was a less attractive choice for performing dynamic and partial reConfiguration due to the lack of an Internal Configuration port. However, a virtual Internal Configuration port, JCAP, has previously been realized by using the external JTAG interface. This paper presents an approach for Internal Configuration readback for failure detection and task migration by extending the JCAP core functionality. The paper also presents the first results from implementing self-reConfiguration over JCAP.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
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FPL - Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
M. Dreschmann - One of the best experts on this subject based on the ideXlab platform.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
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FPL - Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
L. Chen - One of the best experts on this subject based on the ideXlab platform.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
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FPL - Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an Internal Configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual Internal Configuration port for the Spartan III family of FPGAs. The Configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.