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Sc Dsp - One of the best experts on this subject based on the ideXlab platform.
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Freescale Semiconductor Data Sheet
2013Co-Authors: Four Starcore, Sc DspAbstract:unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable Interrupt Controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM Controllers, device configuration control and status registers, and other targets. 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. 96 Kbyte boot ROM. Three input clocks (one global and two differential). Five PLLs (three global and two Serial RapidIO PLLs). Two DDR Controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per Controller) and support for DDR2 and DDR3. • DMA Controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97
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Freescale Semiconductor Data Sheet
2013Co-Authors: Four Starcore, Sc DspAbstract:unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable Interrupt Controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM Controllers, device configuration control and status registers, MAPLE-B, and other targets. 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. 96 Kbyte boot ROM. Three input clocks (one global and two differential). Five PLLs (three global and two Serial RapidIO PLLs). Multi-Accelerator Platform Engine for Baseband (MAPLE-B) with a programmable system interface, Turbo decoding, Viterbi decoding, and FFT/iFFT and DFT/iDFT processing. MAPLE-B can be disabled when not required to reduce overall power consumption. Two DDR Controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per Controller) and support for DDR2 and DDR3. • DMA Controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97
Four Starcore - One of the best experts on this subject based on the ideXlab platform.
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Freescale Semiconductor Data Sheet
2013Co-Authors: Four Starcore, Sc DspAbstract:unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable Interrupt Controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM Controllers, device configuration control and status registers, and other targets. 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. 96 Kbyte boot ROM. Three input clocks (one global and two differential). Five PLLs (three global and two Serial RapidIO PLLs). Two DDR Controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per Controller) and support for DDR2 and DDR3. • DMA Controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97
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Freescale Semiconductor Data Sheet
2013Co-Authors: Four Starcore, Sc DspAbstract:unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable Interrupt Controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM Controllers, device configuration control and status registers, MAPLE-B, and other targets. 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. 96 Kbyte boot ROM. Three input clocks (one global and two differential). Five PLLs (three global and two Serial RapidIO PLLs). Multi-Accelerator Platform Engine for Baseband (MAPLE-B) with a programmable system interface, Turbo decoding, Viterbi decoding, and FFT/iFFT and DFT/iDFT processing. MAPLE-B can be disabled when not required to reduce overall power consumption. Two DDR Controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per Controller) and support for DDR2 and DDR3. • DMA Controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97
Кулик, Анатолій Ярославович - One of the best experts on this subject based on the ideXlab platform.
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Device for transmitting discrete data with wideband modulation of signals
Державне підприємство "Український інститут промислової власності" (УКРПАТЕНТ), 2005Co-Authors: Кулик, Анатолій Ярославович, Kulyk, Anatolii YaroslavovychAbstract:Пристрій для передавання дискретної інформації в умовах широкосмугової модуляції містить персональний комп'ютер у складі центрального процесора, оперативного та постійного запам'ятовувальних пристроїв та носія інформації, послідовний інтерфейс, програмований контролер переривань, вхід INT0 якого підключений до виходу формування сигналу переривання послідовного інтерфейсу, програмований таймер, генератор опорної частоти, вихід якого з'єднаний з тактовими входами CLK першого СТ1 та нульового СТ0 лічильників програмованого таймера, та канал зв'язку. Пристрій також містить генератор функцій Хаара, схема І, два джерела опорної напруги, два компаратори, дві логічні схеми АБО, два тригери та паралельний інтерфейс.Предлагаемое устройство для передачи дискретной информации с широкополосной модуляцией сигналов содержит персональный компьютер с последовательным интерфейсом и программируемым контроллером прерываний, программируемый таймер, генератор сигнала опорной частоты, линию связи и, дополнительно, генератор функций Хаара, логический элемент И, два источника опорного напряжения, два компаратора, два логических элемента ИЛИ, два триггера и параллельный интерфейс. Вход INT0 контроллера прерываний соединен с выходом сигнала прерывания в схеме последовательного интерфейса. Выход генератора сигнала опорной частоты соединен с тактовыми входами счетчиков CT0 и CT1 в схеме таймера.The proposed device for transmitting discrete data with wideband modulation of signals contains a personal computer with a serial interface and a programmable Interrupt Controller, a programmable timing unit, a reference-frequency oscillator, and additionally, a Haar function generator, an AND logic element, two reference voltage sources, two comparators, two OR logic elements, two triggers, and a parallel interface. The INT0 input of the Interrupt Controller is connected to the output for an Interrupt signal in the serial interface circuit. The output of the reference-frequency oscillator is connected to the timing inputs of the CT0 and CT1 in the timing unit circuit
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Method for coding and transmitting data with protection against unauthorized access and a device for the realization of the method
Державне підприємство "Український інститут промислової власності" (УКРПАТЕНТ), 2004Co-Authors: Кулик, Анатолій Ярославович, Гармаш, Володимир Володимирович, Kulyk, Anatolii YaroslavovychAbstract:Спосіб кодування та передавання інформації із захистом включає в себе зчитування з носія стандартного блока даних і передавання по каналу зв'язку. На передавальному боці числовими методами розраховують функції Хаара, програмним шляхом розраховують номери відповідних функцій, які апроксимують зчитаний стандартний блок, вибирають таку послідовність номерів функцій, яка є мінімальною для зворотного перетворення із забезпеченням заданої похибки. Отримані номери функцій Хаара передають через послідовний інтерфейс і модем до каналу зв'язку; на приймальному боці приймають розмір стандартного блока, виконують приймання номерів функцій та відновлення самих функцій Хаара, їх зворотне перетворення та відновлення інформації. Пристрій для передавання та приймання дискретної інформації із захистом містить канал передачі інформації, послідовний інтерфейс, програмований контролер переривань, персональний комп'ютер у складі центрального процесора, оперативного запам'ятовувального пристрою, системного каналу і носія інформації, та модем. До складу персонального комп'ютера додатково введений постійний запам'ятовувальний пристрій.Предлагаемый способ кодирования и передачи данных с защитой от неразрешенного доступа заключается в том, что в передатчике канала связи определяют функции Хаара для кодирования передаваемого блока данных и задают такую последовательность функций Хаара с соответствующими номерами, при которой обеспечивается минимальный объем вычислительных операций при декодировании данных с заданной погрешностью, передают данные о номерах функций Хаара, представленных в заданной последовательности, по каналу связи, определяют функции Хаара в приемнике канала связи, используя данные о номерах функций в последовательности, и обеспечивают декодирование принятых данных с помощью обратного преобразования функций Хаара. Предлагаемое устройство для осуществления способа содержит канал связи, средства последовательного интерфейса, программируемый контроллер прерываний, персональный компьютер с модемом и, дополнительно, постоянное запоминающее устройство в составе персонального компьютера.The proposed method for coding and transmitting data with protection against unauthorized access consists in determining Haar functions for coding the data block to be transmitted and defining such a sequence of the Haar functions, with the corresponding numbers, that provides the minimal number of computing operations in decoding data with a specified error, transmitting the data for the Haar function numbers that are presented in the said sequence over the communication channel, determining the Haar function in the receiver of the communication channel by using the data for the function numbers in the sequence, and decoding the received data by the inverse conversion of the Haar functions. The proposed device for the realization of the method contains a communication channel, a serial interface facilities, a programmable Interrupt Controller, a personal computer with a modem, and additionally, a read-only memory unit in the personal computer
Xinan Wang - One of the best experts on this subject based on the ideXlab platform.
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design of an optimized low latency Interrupt Controller for ims dpu
International Conference on ASIC, 2013Co-Authors: Zijia Guo, Teng Wang, Xinan WangAbstract:Interrupt handling mechanism is an important function for multi-core system to work collaboratively. In this paper, an optimized low-latency Interrupt Controller is proposed to support a multi-core system IMS-DPU for high performance medical electronics equipment. Utilizing two Interrupt models, the Interrupt Controller implements three different kinds of Interrupts, shared peripheral Interrupt (SPI), private peripheral Interrupt (PPI) and software generated Interrupt (SGI). The main feature of the Controller is to distribute multiple Interrupts across the cores of a multi-core system. In addition, our architecture supports several advanced features like Interrupt pending and active state, Interrupt preemption and nesting, Interrupt grouping and security extension. The design in this study puts forward special optimization for performance enhancement in hardware structures, with the aim to support the combination of software stack and hardware stack, tail chaining and later arrivals. FPGA prototyping results justify the design. It is finally implemented with CSMC 180nm technology with 6.01K logic gates at working frequency of 200MHz.
Hu Ziyi - One of the best experts on this subject based on the ideXlab platform.
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Design of an Optimized Low-latency Interrupt Controller for IMS-DPU
2013Co-Authors: Guo Zijia, Wang Teng, Wang Xin-an, Hu ZiyiAbstract:Interrupt handling mechanism is an important function for multi-core system to work collaboratively. In this paper, an optimized low-latency Interrupt Controller is proposed to support a multi-core system IMS-DPU for high performance medical electronics equipment. Utilizing two Interrupt models, the Interrupt Controller implements three different kinds of Interrupts, shared peripheral Interrupt (SPI), private peripheral Interrupt (PPI) and software generated Interrupt (SGI). The main feature of the Controller is to distribute multiple Interrupts across the cores of a multi-core system. In addition, our architecture supports several advanced features like Interrupt pending and active state, Interrupt preemption and nesting, Interrupt grouping and security extension. The design in this study puts forward special optimization for performance enhancement in hardware structures, with the aim to support the combination of software stack and hardware stack, tail chaining and later arrivals. FPGA prototyping results justify the design. It is finally implemented with CSMC 180nm technology with 6.01K logic gates at working frequency of 200MHz.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000341774100020&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701EICPCI-S(ISTP)
